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Multiple-row concurrent readout scheme for high-speed CMOS image sensor with backside illumination

A counter and arithmetic technology, applied in the arithmetic counter circuit, configuration and application field of high-performance CMOS image sensor, can solve the problem of full well and so on

Active Publication Date: 2013-04-17
OMNIVISION TECH INC
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Problems solved by technology

Current charge-coupled devices (CCDs) and CMOS sensors cannot achieve this range due to full well limitations and noise floor limitations typically around 60~70dB

Method used

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  • Multiple-row concurrent readout scheme for high-speed CMOS image sensor with backside illumination
  • Multiple-row concurrent readout scheme for high-speed CMOS image sensor with backside illumination
  • Multiple-row concurrent readout scheme for high-speed CMOS image sensor with backside illumination

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Embodiment approach

[0072] Pixel Implementation, Row Drivers, and Timing

[0073] figure 2 An example of a pixel array in a multi-row simultaneous readout scheme according to an embodiment of the present invention is illustrated. exist figure 2 In the embodiment in , two shared non-row selection pixels are used as an example. In other embodiments, other pixel structures and variations may be used. One logical unit cell 109 (outlined with a dotted line) contains two pixels that have the same row decoder address (e.g., row ) and share the same row driver signal, the same transmit (TX) line, and the same reset (RST) and set (RS) signals.

[0074] exist figure 2 , pixels are arranged in two columns (for example, columns C1 and C2 ) and six rows (for example, rows R1 , R2 . . . R6 ). The illustrated embodiment of each pixel circuit includes a photodiode PD, transfer transistor Tl, reset transistor T2, and select transistor T3. During operation, transfer transistor T1 receives a tran...

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Abstract

A system, method and apparatus implementing a multiple-row concurrent readout scheme for high-speed CMOS image sensor with backside illumination are described herein. In one embodiment, the method of operating an image sensor starts acquiring image data within a color pixel array and the image data from a first set of multiple rows in the color pixel array is then concurrently readout. Concurrently reading out the image data from the first set of multiple rows includes concurrently selecting a first portion of the image data from the first set by first readout circuitry and a second portion of the image data from the first set by second readout circuitry. The first and second portions of the image data from the first set are different and the first and second readout circuitries are also different. Other embodiments are also described.

Description

[0001] Cross References to Related Applications [0002] This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Application No. 61 / 545,993, filed October 11, 2011, which is specifically incorporated herein by reference in its entirety. technical field [0003] Embodiments of the present invention generally relate to a system, method, and apparatus that implement a multi-row simultaneous readout scheme for a high-speed CMOS image sensor with backside illumination. Another embodiment of the present invention generally relates to a system, method and apparatus that implements a high dynamic range sub-sampling architecture. Yet another embodiment of the present invention generally relates to a system and apparatus implementing an arithmetic counter circuit for a high performance CMOS image sensor. Background technique [0004] High-speed image sensors have been widely used in many applications in different fields, including the automotive field, the field ...

Claims

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Application Information

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IPC IPC(8): H04N5/374H04N5/3745H04N5/378
CPCH04N25/531H04N25/46H04N25/57H04N25/77H04N25/78H04N25/75
Inventor 莫要武徐辰瞿旻代铁军骆晓东王睿
Owner OMNIVISION TECH INC
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