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Strained silicon channel semiconductor structure and fabrication method thereof

A strained silicon and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems affecting transistor performance and carrier reduction

Active Publication Date: 2016-12-14
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, due to the limitations of the inherent physical properties of the material, the reduction in the size of the gate, source, and drain will reduce the amount of carriers that determine the magnitude of the current in the transistor element, thereby affecting the performance of the transistor.

Method used

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  • Strained silicon channel semiconductor structure and fabrication method thereof
  • Strained silicon channel semiconductor structure and fabrication method thereof
  • Strained silicon channel semiconductor structure and fabrication method thereof

Examples

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Embodiment Construction

[0052] Figure 2 to Figure 8 It is a schematic flow diagram of a method for fabricating a strained silicon semiconductor structure according to a preferred embodiment of the present invention, and the text will refer to these diagrams in order to illustrate the fabrication process of the strained silicon semiconductor structure of the present invention. For convenience of description, each figure defines a horizontal direction H parallel to the surface of the substrate 10 and a vertical direction V perpendicular to the surface of the substrate 10 .

[0053] First, please refer to figure 2 In the method, a substrate 10 is provided, and the substrate 10 can be a semiconductor substrate, including but not limited to a silicon wafer or a silicon-on-insulator (SOI) substrate. A plurality of gate structures 12 are disposed on the substrate 10 . Each gate structure 12 includes a gate conductive layer 14, a gate dielectric layer 16 disposed between the surface of the substrate 10 a...

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Abstract

The invention discloses a strained silicon channel semiconductor structure and a manufacturing method thereof. The method includes: providing a substrate; forming at least one gate structure on the substrate; performing an etching process to the substrate on the side of the gate structure At least one groove is formed in the groove, the sidewall of the groove is concave toward the direction of the gate structure and forms an angle with the horizontal plane; and a pre-baking process is performed to change the shape of the groove so that the sidewall of the groove is The angle between the horizontal plane becomes larger.

Description

technical field [0001] The invention relates to a strained silicon channel semiconductor structure and a manufacturing method thereof, in particular to a strained silicon channel semiconductor structure with better carrier mobility and a manufacturing method thereof. Background technique [0002] With the development of semiconductor devices towards miniaturization, the dimensions of the gate, source, and drain in the transistor are also continuously reduced along with the reduction of the feature size. However, due to the limitations of the inherent physical properties of the material, the reduction in the size of the gate, source, and drain will reduce the amount of carriers that determine the current in the transistor element, thereby affecting the performance of the transistor. Therefore, increasing the carrier mobility to increase the speed of the transistor has become a major topic in the field of semiconductor technology. [0003] In order to increase carrier mobilit...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L27/092H01L21/8238
Inventor 杨建伦郭敏郎廖晋毅简金城詹书俨吴俊元
Owner UNITED MICROELECTRONICS CORP
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