Single Instruction Multiple Data Arithmetic Unit supporting multiple data types
A technology of single instruction multiple data and arithmetic unit, applied in the field of arithmetic unit, can solve the problems of poor applicability, arithmetic unit cannot support multiple data widths, etc., and achieve the effect of good applicability
Inactive Publication Date: 2016-06-22
ZHEJIANG UNIV
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[0006] In order to overcome the shortcomings of existing arithmetic units that cannot support multiple data widths and poor applicability, the present invention provides a single instruction multiple data arithmetic unit that can effectively support multiple data widths and has good applicability and supports multiple data types
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[0033] The present invention will be further described below in conjunction with the accompanying drawings.
[0034] refer to Figure 1 to Figure 9 , a single instruction multiple data arithmetic unit supporting multiple data types, the arithmetic unit includes N atomic operation arrays (11), N is any positive integer, and each atomic operation array uses an adder to realize various bit widths For arithmetic operations on data, the atomic operation array (11) includes:
[0035] An operand preparation unit (21), configured to perform inversion, sign bit extension, bit width extension, and carry extension operations on the input source operand according to the input operation type and data type information, and output the intermediate operand;
[0036] An addition operation unit (22), used to receive the intermediate operand from the operand preparation unit, complete the addition operation, and output the addition operation result;
[0037] A rounding operation unit (23), use...
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A single-instruction multi-data arithmetic unit supporting various data types comprises N atom operation arrays. Each atom operation array comprises an operand preparation unit, an additive operation unit, a round-off operation unit, a saturation operation unit and a result encapsulation unit. The operand preparation unit is used for carrying out operation on an input source operand and outputting a middle operand according to input information of operation types and data types; the additive operation unit is used for receiving the middle operand and finishing additive operation and outputting a result of the additive operation; the round-off operation unit is used for carrying out round-off operation on the result of the additive operation according to the input information of the operation types and the data types, and outputting a result of the round-off operation. The saturation operation unit is used for carrying out saturation operation on the result of the additive operation according to the input information of the operation types and the data types. The result encapsulation unit is used for selecting the input result of the round-off operation unit or the saturation operation unit, and saturating a middle result into a final datum according to the information of the data types. The ingle-instruction multi-data arithmetic unit can effectively support various data widths, and applicability is good.
Description
technical field [0001] The invention relates to a multimedia computing unit, in particular to an arithmetic unit. Background technique [0002] Multimedia applications usually refer to operations such as capture, storage, transformation, transmission, encoding and decoding of multimedia objects such as text, audio, static images, two-dimensional graphics, three-dimensional graphics, animations, and full-motion videos. The biggest feature of multimedia signals is the small data bit width and large data throughput. [0003] Single Instruction Multiple Data (SIMD) technology refers to the realization of multiple data stream operations by simultaneously controlling two or more parallel processing units through a controller. The same operation is performed in parallel by the data units, so that the parallel operation can be realized in time. [0004] Most of the existing 40-bit arithmetic operation units can only realize one 32-bit operation or one 16-bit operation or one 8-bit...
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IPC IPC(8): G06F9/38
Inventor 严晓浪仇径孟建熠陈志坚
Owner ZHEJIANG UNIV