A multi-slot transceiver

Abstract

The invention discloses a multi-slot transceiver. The multi-slot transceiver comprises a frequency generation unit. The frequency generation unit a control unit, a first frequency synthesis unit, a second frequency synthesis unit, a third frequency synthesis and a frequency processing unit, wherein the first frequency synthesis unit is used for outputting a first high frequency local oscillator; the second frequency synthesis unit is used for outputting a second high frequency local oscillator; the third frequency synthesis unit is used for outputting an intermediate frequency local oscillator; and the frequency processing unit is used for using the first high frequency local oscillator and the intermediate frequency local oscillator as two local oscillators of a superheterodyne receiver in a receiving timeslot respectively, processing the first high frequency local oscillator and the intermediate frequency local oscillator in a transmission timeslot, using a processed signal as a transmission local oscillator, and using the second high frequency local oscillator as a preparatory local oscillator of frequency hopping in the next receiving or transmission timeslot. According to the technical scheme, the multi-slot transceiver occupies a small space, and is low in cost and power consumption, a few serial peripheral interface (SPI) resources are occupied, the interference of transmission of a same-frequency signal with reception in a same-frequency reception-to-transmission working mode of adjacent timeslots can be avoided, and noise signals generated by the modulation of a modulator in a different-frequency transmission-to-transmission working mode of adjacent timeslots are easy to filter.

Description

Technical field [0001] The present invention relates to the field of communications, in particular to a multi-slot transceiver. Background technique [0002] With the increasing development of science and technology and the rapid development of wireless communication, the development and application opportunities and challenges of TDMA (Time Division Multiple Address) systems coexist. Stabilizing the performance of TDMA system applications can help maximize the value of the TDMA system. For TDMA systems with multi-slot transceivers, such as TETRA (terrestrial trunking communication system) Gateway and repeater systems, their working time slots are complex, and continuous time slot rates of receiving and forwarding, sending and forwarding may occur. Sending-receiving, receiving-receiving working mode. [0003] Due to the limitation of lock time, it is impossible to achieve this multi-slot transceiver conversion function with only a single phase-locked loop. It is necessary to use ...

AI Technical Summary

Problems solved by technology

[0005] 1. Adopt 5 frequency synthesis units, and each frequency synthesis unit includes a phase-locked loop chip and a voltage-controlled oscillator. The phase-locked loop chip is, for example, PLL (Phase loop locked, phase-locked loop) 1, PLL2, PLL3, and PLL4 (Fig. The PLL4 shown in is a dual phase-locked loop), and the voltage-controlled oscillators are, for example, TXVCO (Voltage Control Oscillator, voltage-controlled oscillator) 1, TXVCO2, RXVCO1, RXVCO2, and IFVCO. Therefore, the occupied PCB area, cost and power consumption are relatively small Large, and it needs to occupy too many SPI resources;

[0006] 2. In the same-frequency receiving and forwarding mode of adjacent time slots, due to the need for t before the end of the receiving time slot 0 Turn on the frequency synthesis unit of the transmitter at all times, for example, turn on the phase-locked loop chip PLL1 and the voltage-controlled oscillator TXVCO1, and need t before the end of the receiving time slot 1 The modulator is initialized at all times, so when the receiving time slot is not over, the frequency signal generated by the frequency synthesis unit will be transmitted to the radio frequency unit after being passed through the modulator, so it is easy to cause co-channel interference with reception;

[0007] 3. In the inter-frequency transmission and forwarding mode of adjacent time slots, it is assumed that the phase-locked loop chip PLL1 and voltage-controlled oscillator TXVCO1 are working in the previous transmission time slot, and the phase-locked loop chip PLL2 and voltage-controlled oscillator TXVCO1 are working in the next transmission time slot. Oscillator TXVCO2 is working, it needs to be t before the end of the previous transmission slot 0 If the phase-locked loop chip PLL2 and the voltage-controlled oscillator TXVCO2 are turned on at all times, it is easy for the pre-locked local oscillator to leak to the modulator modulation to generate adjacent channel or broadband noise. Moreover, the noise signal leaked to the modulator modulation is very close to the transmitted signal. not easy to filter out

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