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Systems and methods for inter-unit interference cancellation

A technology of memory cells and word lines, applied in digital memory information, instruments, static memory, etc., can solve the problem that the threshold voltage cannot be directly read out

Inactive Publication Date: 2018-08-10
MARVELL ASIA PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Threshold voltage V T cannot be read directly

Method used

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  • Systems and methods for inter-unit interference cancellation
  • Systems and methods for inter-unit interference cancellation
  • Systems and methods for inter-unit interference cancellation

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Experimental program
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Embodiment Construction

[0055] This disclosure relates to eliminating inter-cell interference in flash memory. In flash memory, when new data is written in memory cells along a word line, the newly written data affects data written earlier in memory cells along adjacent word lines. Thus, data written earlier in memory cells along adjacent word lines experiences inter-cell interference from newly written data.

[0056] Inter-unit interference is data dependent. That is, inter-cell interference depends on the data pattern of newly written data. To correct for the effect of inter-cell interference on data stored in memory cells along a word line, the memory cells along the word line can be read repeatedly. Information obtained by repeatedly reading memory cells along a word line is used to decode data stored in the memory cells along the word line.

[0057] The present disclosure relates to eliminating the effect of inter-cell interference on data stored in memory cells along a word line by reading t...

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Abstract

Each embodiment of the present invention generally involves interference between units.Specifically, one method involves the first memory unit that chooses the first and first line positioning of the memory array.This method further includes the second storage unit of the second -digit positioning of the first line of the first line of the (i), (ii) near the first line line of the first line line,EssenceSelect the position of the second memory unit based on the predetermined sequence of a programming memory unit.This method further includes writing data in the first memory unit, and then writing data in the second memory unit and reading the first memory unit and the second memory unit.This method further includes one or more states of the second memory that causes interference to the first memory unit.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Provisional Application No. 61 / 576,291, filed December 15, 2011. The entire disclosures of the applications cited above are hereby incorporated by reference. technical field [0003] The present disclosure relates generally to semiconductor memory, and more particularly to glitch cancellation in flash memory. Background technique [0004] The background description provided here is for the purpose of generally presenting the context of the disclosure. The work of the present inventors is neither expressly nor implicitly admitted as relative to prior art for this disclosure. [0005] Memory integrated circuits (ICs) include memory arrays. A memory array includes memory cells arranged in rows and columns. The memory cells may include cells of volatile memory or non-volatile memory. Volatile memory loses data stored in the memory cells when power is removed from the memory ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06
CPCG11C11/5642G11C16/3418G11C16/3427G11C16/26G11C16/04G11C16/3404G11C16/34
Inventor S·K·奇拉帕加里陈振钢G·伯德
Owner MARVELL ASIA PTE LTD