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Double-depth shallow-trench isolation channel preparation method

A technology of shallow trench isolation and trench isolation, which is applied in the field of preparation of double-depth shallow trench isolation trenches, and can solve problems such as step-like height differences in hard mask layers

Inactive Publication Date: 2013-09-11
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

[0012] The purpose of the present invention is to provide a method for preparing a double-depth shallow trench isolation trench, which can avoid the double slope of the side wall of the shallow trench isolation trench in the prior art while forming a double-depth shallow trench isolation trench structure Topography and step-like height difference of the hard mask layer

Method used

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  • Double-depth shallow-trench isolation channel preparation method
  • Double-depth shallow-trench isolation channel preparation method
  • Double-depth shallow-trench isolation channel preparation method

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preparation example Construction

[0042] Please refer to figure 2 , the present invention proposes a method for preparing a double-depth shallow trench isolation trench, comprising the following steps:

[0043] S1, providing a substrate including a photosensitive region and a logic region, on which a hard mask layer and a first photoresist layer are sequentially formed, and the first photoresist layer is formed with a deep STI in the logic region pattern;

[0044] S2, using the first photoresist layer and the hard mask layer as a mask, performing deep STI etching in the logic area, and forming deep and shallow trench isolation grooves in the logic area;

[0045] S3, forming a second photoresist layer on the surface of the device where the deep and shallow trench isolation trenches are formed, the second photoresist layer is formed with a shallow STI pattern in the photosensitive region;

[0046] S4, using the second photoresist layer as a mask, performing shallow STI etching in the photosensitive area to fo...

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Abstract

The invention provides a double-depth shallow-trench isolation channel preparation method. A double-depth shallow-trench isolation channel is prepared by a logic region deep-shallow trench isolation channel process and a light-sensitive region shallow-shallow trench isolation channel process which are completely independent, so that the double-slope appearance of a deep-shallow trench isolation channel is avoided; by the aid of the shallow feature of a shallow-shallow trench isolation channel, a second photoresist layer is directly used as a mask layer for light-sensitive region shallow STI (shallow trench isolation) etching, so that the problem of step height difference formed in a hard mask layer in two passes of STI etching is avoided.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing double-depth shallow trench isolation grooves. Background technique [0002] The Shallow Trench Isolation (STI) process is one of the key processes in the formation of CMOS devices. With the continuous shrinking of the device size, the thickness of the photoresist is limited, but the etching depth of STI does not decrease too much, so that the photoresist It cannot meet the thickness requirement of the STI etching mask layer, so after the 130nm technology node, the silicon nitride hard mask process is widely used in the prior art for STI etching. [0003] At the same time, CIS (CMOS Image Sensor, CMOS image sensor) products based on advanced technology platforms (<65nm) are currently hot spots in the field of chip manufacturing. Its manufacturing process has many differences from traditional logic or memory chips. In the key process of STI, be...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762H01L27/146
CPCH01L21/3081H01L21/3083H01L21/76229
Inventor 杨渝书秦伟黄海辉
Owner SHANGHAI HUALI MICROELECTRONICS CORP