A double-depth shallow trench isolation trench and its preparation method
A technology of shallow trench isolation and isolation trenches, which is applied in radiation control devices, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of poor electrical performance of photosensitive devices and low electrical isolation performance of STI, and achieve improved performance , avoid double-slope morphology, and expand the effect of the process window
Active Publication Date: 2021-07-02
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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Problems solved by technology
[0004] However, in the traditional process of forming a double-depth STI structure, the performance of STI electrical isolation is low, and the electrical performance of the subsequently formed photosensitive device is poor.
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preparation example Construction
[0038] A traditional method for preparing a double-depth shallow trench isolation trench includes the following steps:
[0039] Step S11: See Figure 1a , providing a substrate 10 including a photosensitive region I and a logic region II, and sequentially depositing silicon oxide 11, a silicon nitride hard mask layer 12, and a patterned first photoresist 13 on the substrate 10;
[0040] Step S12: See Figure 1b , the silicon nitride hard mask layer 12 and the silicon oxide 11 are sequentially etched by the first dry etching process, and the etching stops in the substrate 10 at a partial depth, so as to form the first isolation trench 14 and the second isolation trench 14. The first part 15a of the two isolation grooves, the first isolation groove 14 is located in the photosensitive area I, and the first part 15a is located in the logic area II, and the remaining first part 15a is cleaned and removed by an oxygen ashing method and a wet etching process. a photoresist 13;
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The invention provides a double-depth shallow trench isolation trench and a preparation method thereof. The preparation method of the double-depth shallow trench isolation trench includes: providing a substrate on which a hard mask layer and a patterned first photoresist layer; using the patterned first photoresist layer as a mask, etch to form a first opening and a second opening, and then remove the first photoresist layer; form a patterned first photoresist layer on the hard mask layer Two photoresist layers; using the patterned second photoresist layer and hard mask layer as a mask, etch to form the first part of the second isolation groove, and then remove the second photoresist layer; use the hard mask The mold layer is a mask, and the second part of the second isolation groove and the first isolation groove are formed by etching, so that the first isolation groove in the photosensitive area and the second isolation groove in the logic area are formed at the same time, which improves the electrical performance of the photosensitive device , It also improves the performance of STI electrical isolation, and at the same time, reduces the difficulty of the process and expands the process window.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a double-depth shallow trench isolation trench and a preparation method thereof. Background technique [0002] The shallow trench isolation (STI, Shallow Trench Isolation) process is one of the key processes in the formation of CMOS devices. As the device size continues to shrink, the thickness of the photoresist is limited, and the etching depth of STI is not greatly reduced. The photoresist cannot meet the thickness requirement of the STI etching mask layer, so after the 130nm technology node, the silicon nitride hard mask process is widely used in the prior art for STI etching. [0003] At the same time, CIS (CMOS Image Sensor, CMOS image sensor) products based on advanced technology platforms (<65nm) are currently hot spots in the field of chip manufacturing. Since the CIS chip has both a photosensitive area (Pixel) and a surrounding logic area (Logic), so that ...
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IPC IPC(8): H01L21/762H01L27/146
CPCH01L21/76224H01L27/1463H01L27/14687
Inventor 杨渝书伍强李艳丽
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT