Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device, which comprises a substrate, a plurality of gate stacking structures on the substrate, a plurality of gate side wall structures on the two sides of each gate stacking structure, and a plurality of source-drain regions in the substrate on the two sides of each gate side wall structure. The gate stacking structures comprise a plurality of first gate stacking structures and a plurality of second gate stacking structures, wherein each first gate stacking structure comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion barrier layer and a gate filling layer, and the work function is close to a valance band (conduction band) side. Each second gate stacking structure comprises a second gate insulating layer, a modified first work function metal layer, a second work function metal layer and a gate filling layer. The semiconductor device is characterized in that the second work function metal layer comprises injected doping ions for adjusting the work function, and part of the first work function layer which is diffused below the second work function mental layer is used for adjusting a threshold to enable the work function of a gate to be close to the conduction band (valence band) side and to correspond to a first work function, so that the work function of the gate is accurately adjusted.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a MOSFET and a manufacturing method thereof which use metal injection to adjust work function. Background technique [0002] Starting from the 45nm CMOS integrated circuit process, with the continuous reduction of device feature size, in order to suppress the short channel effect, the equivalent oxide thickness (EOT) of the gate insulating dielectric layer in CMOS devices must be reduced simultaneously. However, due to the low (relative) dielectric constant (for example, about 3.9) of the ultra-thin (eg 10nm) conventional oxide layer or oxynitride layer, the insulation performance is difficult to withstand the relatively high field strength in such ultra-small devices, which will cause serious damage. gate leakage. Therefore, the traditional polysilicon (poly-si) / SiON system is no longer applicable. [0003] In view of this, the industry has begun to ...

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Problems solved by technology

[0007] However, this method of adjusting the work function only by controlling the film thickness ratio is no longer suitable for ultra-thin and ultra-small devices due to the large process instability after the film thickness reaches the nanometer level, so it is difficult to rationally optimize the control Threshold Adjustment for Small Devices

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