Semiconductor package structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor packaging structure. The semiconductor packaging structure comprises a redistribution layer, at least one chip and at least one pin, wherein the redistribution layer has a power source input end and a power source output end, the chip is arranged on the redistribution layer and has an active surface, the active surface is in electrical connection with the redistribution layer, a power source input pad of the active surface of the chip is in connection with the power source output end of the redistribution layer correspondingly, the pin is arranged on the redistribution layer, the pin has a connection portion, a first convex portion and a second convex portion, the connection portion connects the first convex portion with the second convex portion, the first convex portion is in electrical connection with the power source input end of the redistribution layer correspondingly, and the second convex portion is in electrical connection with the power source output end of the redistribution layer correspondingly. The pin realizes providing a relatively large contact area, a relatively large cross section area and a prolonged conduction path and can realize an electric buffering effect when a power source is inputted into the chip through the redistribution layer to avoid damage to the chip.

Description

technical field [0001] The invention relates to a semiconductor package structure and a manufacturing method thereof, in particular to a semiconductor package structure with flexible port design. Background technique [0002] In the basic semiconductor packaging structure, the chip is placed on a substrate by wire bonding or flip chip bonding, so that the chip is electrically connected through wires or bumps. connected to the substrate. The flip-chip bonding process is mainly to provide conductive bumps on the pads on the active surface of a chip, and then turn the chip over so that the active surface is disposed on a substrate through the bumps. According to the requirements of different circuit densities, a redistribution layer (RDL) can be provided on the active surface of the chip for circuit re-layout, and then conductive bumps can be provided to complete the electrical connection between the chip and the substrate. [0003] The above-mentioned redistribution layer is...

AI Technical Summary

Problems solved by technology

However, in order to meet the requirements of light, thin and short packaging products, the wire diameter of the redistribution layer lines formed on the active surface of the current chip is quite small, and the circuit density is also relatively concentrated, resulting in conductive bumps passing through the redistribution layer and then to the chip's The current path is relatively short. When an external power supply supplies power to the chip through this current path, the chip may be damaged immediately when the current is too large or a surge occurs.

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