A chip defect detection method

Abstract

The invention relates to a method for detecting chip defects. The method for detecting the chip defects includes the following steps: S1, offering a wafer, wherein a plurality of identical chips are manufactured on the surface of the wafer, and the chips are arranged on the wafer in a matrix mode; S2, selecting a to-be-tested chip, selecting at least two contrast chips according to the to-be-tested chip, wherein the to-be-tested chip and the contrast chips form a chip set, and the chips in the chip set are arranged on the same straight line at equal intervals; S3, obtaining the data image of the to-be-tested chip and the data images of the contrast chips, and S4, respectively comparing the data images of the contrast chips with the data image of the to-be-tested chip one by one. The to-be-tested chip has defects if an abnormal condition is discovered. The distance between every two adjacent chips in the chip set is N, and N is a positive integer.

Description

technical field [0001] The invention relates to a detection method in the manufacturing process of a semiconductor chip, in particular to a chip defect detection method. Background technique [0002] In recent years, with the rapid development of semiconductor integrated circuits, the performance of integrated circuit devices is also rapidly improving. With the improvement of the performance of integrated circuit devices, the manufacturing process has become more and more complicated. Currently, advanced integrated circuit It contains hundreds of process steps. Therefore, a problem in one of the steps will cause the problem of the entire semiconductor integrated circuit chip. It is manifested that the performance of the semiconductor integrated circuit fails to meet the design requirements, and it may even lead to the failure of the entire chip. [0003] Therefore, in the manufacturing process of semiconductor integrated circuits, it is particularly important to detect the p...

AI Technical Summary

Problems solved by technology

The defect detection method disclosed in this patent needs to provide a master substrate and detect the substrate to be inspected based on the master substrate. The implementation of this method needs to rely on an additional master substrate. If damage occurs, it will affect the accuracy of defect detection; moreover, it divides the adjacent die into multiple regions, and detects defects by using the regions as units. Therefore, this detection method only Can roughly detect defects in integrated circuit products, but cannot accurately detect defects

[0010] It can be seen that there is no detection method with high feasibility and high detection accuracy in the existing defect detection methods.

Images