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Chip defect detection method

A detection method and chip defect technology, which is applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve problems such as low detection accuracy, poor detection rate, and low detection rate, so as to improve selection efficiency, The effect of reducing difficulty and increasing success rate

Inactive Publication Date: 2021-08-24
CHONGQING VOCATIONAL INST OF ENG
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AI Technical Summary

Problems solved by technology

However, this method cannot fully detect the defects on the integrated circuit very effectively in the current products with a very high level of circuit integration, and its detection rate is poor.
The reason for this low detection rate is that in highly integrated integrated circuit products, subtle differences in circuit patterns may lead to completely different chip performance, but from a manufacturing point of view, due to the adjacent chips in the product The process conditions in the manufacturing process are very similar, so that the circuit patterns on adjacent chips may be very similar, but there are still relatively large differences in the scope of the entire silicon chip. Therefore, it is very difficult in continuous comparison operations. It is difficult to detect all the points with slight differences in the entire silicon wafer range, and the detection accuracy is low

Method used

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Examples

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Embodiment 1

[0042] Such as figure 1 As shown, chip A 1 is selected as the chip to be tested, and the geometric center of chip A 1 is used as the origin as a plane rectangular coordinate system. The X axis of the plane rectangular coordinate system is perpendicular to the opening direction of the wafer alignment mark, and the Y axis is perpendicular to the opening direction of the wafer alignment mark. The opening direction of the wafer alignment mark is parallel, and B chip 2 and C chip 3 on the four quadrant angle bisectors of the plane Cartesian coordinate system are selected as comparison chips; then the wafer is scanned by an optical detection device equipped with high sensitivity, Obtain the optical image of the chip on the wafer, convert the optical image to form a data image, and the data image is represented by different bright and dark gray scales; for example figure 2 A. figure 2 B and figure 2 As shown in C, there is a difference between the data image of A chip 1 and the ...

Embodiment 2

[0044] Such as image 3 As shown, the D chip 4 is selected as the chip to be tested, and the geometric center of the D chip 4 is used as the origin of the plane Cartesian coordinate system. The X axis of the plane Cartesian coordinate system is perpendicular to the opening direction of the wafer alignment mark, and the Y axis is perpendicular to the opening direction of the wafer alignment mark. The opening direction of the wafer alignment mark is parallel, and E chip 5, F chip 6, G chip 7, and H chip 8 on the four quadrant angle bisectors of the plane Cartesian coordinate system are selected as comparison chips; The detection equipment scans the wafer to obtain the optical image of the chip on the wafer, and converts the optical image to form a data image. The data image is represented by different bright and dark gray scales; for example Figure 4 A. Figure 4 B. Figure 4 C. Figure 4 D and Figure 4 As shown in E, there is a difference between the data image of D chip ...

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Abstract

The invention discloses a chip defect detection method, and relates to the technical field of semiconductors. The method comprises the steps of providing a wafer of which the surface is provided with a plurality of same chips, wherein the plurality of same chips are arranged on the wafer in a matrix manner; then selecting a chip to be tested, establishing a virtual rectangular plane coordinate system with the geometric center of the chip to be tested as an original point, selecting the chips on the four quadrant angular bisectors of the rectangular plane coordinate system as comparison chips, and selecting at least two comparison chips; acquiring the data images of the to-be-detected chip and the comparison chips; and finally, comparing the data image of each comparison chip with the data image of the to-be-detected chip one by one, and if abnormity is found, determining that the to-be-detected chip has defects. According to the present invention, the defect that the defects of the chips are difficult to detect due to the fact that the adjacent chips are too similar during detection can be overcome, the success rate of wafer defect detection is greatly improved, and therefore the real situation of the defects of the detected wafer can be more accurately reflected.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip defect detection method. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, semiconductor chips are developing towards higher integration. The higher the integration of semiconductor chips, the more complicated the manufacturing process is. The current advanced integrated circuit manufacturing process generally contains hundreds of process steps. Therefore, a problem in one of the steps will cause problems in the entire semiconductor chip. , which shows that the performance of the integrated circuit fails to meet the design requirements, and in serious cases may lead to the failure of the entire chip. [0003] Therefore, it is particularly important to find out the problems existing in the product man...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66
CPCH01L22/12H01L22/24
Inventor 贺晓辉李迈克石磊陈耿
Owner CHONGQING VOCATIONAL INST OF ENG
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