FPGA-based irig-b code encoding and decoding system and its encoding and decoding method
A decoding system and encoding technology, applied in the application of multi-bit parity error detection coding, error correction/detection using block codes, data representation error detection/correction, etc., can solve the problem that the accuracy of decoding functions cannot be solved get test etc.
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specific Embodiment approach 1
[0040] Specific implementation mode 1: see figure 1 This embodiment is described. The FPGA-based IRIG-B code encoding and decoding system described in this embodiment includes a GPS / Beidou dual system module 1, an FPGA2, a single-chip microcomputer 3, a DAC chip 4, a comparator chip 5, and a host computer 6. and PCI riser card 7,
[0041] FPGA2 embedded storage control module 2-1, AC code coding control logic module 2-2, DC code coding control logic module 2-3, DC decoding control logic module 2-4 and AC code decoding control logic module 2-5 ,
[0042] The GPS / Beidou dual system module 1 is used to output time information and send it to the single-chip microcomputer 3 and the storage control module 2-1 at the same time,
[0043] The storage control module 2-1 is used to use the received time information as the original time source, and is also used to input the original time source to the host computer 6 through the PCI adapter card 7,
[0044] The single-chip microcompute...
specific Embodiment approach 2
[0053] Embodiment 2: This embodiment is a further limitation of Embodiment 1. The DAC chip 4 is implemented by a DAC7714, and the DAC7714 is a 12-bit serial input D / A converter.
specific Embodiment approach 3
[0054] Embodiment 3: This embodiment is a further limitation of Embodiment 1, and the comparator chip 5 is a zero-crossing comparator chip.
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