Method measuring interlayer offset of printed circuit board (PCB) and in-process PCB

Abstract

The invention provides a method measuring the interlayer offset of a PCB and the in-process PCB. The method comprises that reference windows whose apertures increase progressively with equal differences are formed in a metal layer at the bottom layer of the in-progress PCB; dielectric layers and metal layers are laminated on the metal layer alternatively; measurement figures and reference windows are formed in the laminated metal layer, wherein the amount of the measurement figures of the laminated metal layer equals to the sum of the amount of the reference windows and the amount of the measurement figures of an adjacent metal layer, and the centers of the measurement figures of the laminated metal layer are aligned with the centers of the reference windows and the centers of the measurement figures of the adjacent metal layer; and metal measurement holes penetrating through the dielectric layer are formed in each dielectric layer, the measurement hole is positioned between the aligned measurement figures and between the aligned measurement figure and reference window in the metal layers at two sides of the dielectric layer, the measurement hole is electrically connected with the measurement figures at two sides, and metal of the reference window in the minimal aperture is electrically connected with the measurement figure which is aligned with the reference window. The interlayer offset is determined by detecting electrical connection states between the measurement figures and the equal difference of the reference windows.

Description

technical field [0001] The invention relates to the detection field of a circuit board PCB, in particular to a method for measuring offset between PCB layers and a PCB in-process. Background technique [0002] During the manufacturing process of a multi-layer PCB, multiple insulating plates covered with copper foil are pressed together to form a multi-layer structure of the PCB. The electrical connection between each layer is realized through the metal hole wall of the insulating plate. [0003] During the lamination process of multi-layer PCB, under the action of pressure, there will be a position shift between the layers. If these position offsets are large, the electrical connectivity between the layers of the PCB will be reduced, and even an open circuit or short circuit between the layers will occur, resulting in defective PCBs. Therefore, it is necessary to frequently detect the interlayer offset of the laminated PCB, and control the offset within a threshold range. ...

AI Technical Summary

Problems solved by technology

[0006] The present invention aims to provide a method for measuring the offset between PCB layers and the PCB in-process to solve the problem that the above-mentioned technology cannot detect the offset between two adjacent layers

Images