Board level circuit testing model automatic generation method

A board-level circuit, automatic generation technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems affecting the accuracy of fault isolation rate, large workload, high error rate, etc., to save manpower and Time spent, reduced number of cross-connections, easy to observe the effect of analysis

Inactive Publication Date: 2013-11-20
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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Problems solved by technology

[0008] Another disadvantage of manual modeling is that it is prone to errors
Due to the large number of components and parameters in the system and the heavy workload, manually filling in such a

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  • Board level circuit testing model automatic generation method
  • Board level circuit testing model automatic generation method
  • Board level circuit testing model automatic generation method

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Example Embodiment

[0049] Example

[0050] The method for automatically generating a testability model of a board-level circuit of the present invention includes the following steps:

[0051] Step 1: Obtain board-level circuit information;

[0052] The board-level circuit consists of multiple circuit boards connected together. Each circuit board can contain multiple failure modes, and each failure mode is defined as a failure module of the circuit board. The board-level circuit testability models are composed of modules and their connection methods. The modules include fault modules and measuring point modules. The information required for the generation of the board-level circuit testability model includes the information of each layer of the circuit board, the fault attributes of the faulty modules contained in each layer of the circuit board, the test attributes of the test point modules, and the directional propagation relationship between the faulty modules. The fault attributes of a faulty mod...

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Abstract

The invention discloses a board level circuit testing model automatic generation method. According to the board level circuit testing model automatic generation method, an XML label is arranged for board level circuit information, the board level circuit information is stored as an XML file, the connecting mode among modules in each layer of circuit board is stored as an adjacent matrix, all the modules of each layer of circuit board are ranked according to the connecting relation recorded in the adjacent matrix, position coordinates of each module are determined in sequence according to an obtained module sequence to complete an initial layout of a model of each layer of circuit board, the number of cross connecting lines between two adjacent lines is reduced to the minimum through the method of layout optimization, and the final layout of the model of each layer of circuit board is obtained. Through the board level circuit testing model automatic generation method, the board level circuit testing model can be automatically generated, the workload for staff is lightened, and the obtained board level circuit testing model is clear and easy to observe and analyze through the module ranking and layout optimization.

Description

technical field [0001] The invention belongs to the technical field of testability models of board-level circuits, and more specifically, relates to a method for automatically generating testability models of board-level circuits. Background technique [0002] In the current semiconductor integrated circuit technology, various circuit functional modules are packaged in the form of printed circuit boards, and board-level circuit modules are combined into complex electronic systems. In order to ensure the safety and efficient operation of systems (such as spacecraft and civil aviation aircraft), when the system is abnormal, it is necessary to quickly locate the faulty board-level circuit and replace the entire board so that the system can quickly resume operation. Therefore, the concept of design for testability is proposed. In the design stage, the post-test maintenance of the product is considered, and the requirement of reducing the cost of test maintenance is included in t...

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Application Information

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IPC IPC(8): G06F17/50G06F9/44
Inventor 杨成林严俊豪龙兵
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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