A half-rate clock-data recovery circuit based on phase-selective interpolation
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A technology of clock data recovery and phase selection, applied in the direction of electrical components, automatic power control, etc., can solve the problems of increasing the difficulty of digital controller design, redundant phase selection/interpolation circuits, etc., and achieve the goal of reducing design difficulty and reducing scale Effect
What is AI technical title?
AI technical title is built by PatSnap AI team. It summarizes the technical point description of the patent document.
A technology of clock data recovery and phase selection, applied in the direction of electrical components, automatic power control, etc., can solve the problems of increasing the difficulty of digital controller design, redundant phase selection/interpolation circuits, etc., and achieve the goal of reducing design difficulty and reducing scale Effect
CN103414464BActive 📅 Publication Date: 2016-08-17NANJING UNIV OF POSTS & TELECOMM
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[0023] In order to further illustrate the advantages of the present invention and the specific technical means adopted, the specific implementation of a phase-selective interpolation-based half-rate clock data recovery circuit of the present invention will be further described in detail below in conjunction with the accompanying drawings.
[0024] The half-rate clock data recovery circuit based on the phase selection interpolation type of the present invention, the clock data recovery circuit includes a half-rate Bang-Bang type phase detector, a digital filter, a digital controller, a phase selector, a phase interpolator, and outer ring reference clock;
[0025] The half-rate Bang-Bang type phase detector receives the input data and the clock signals Clk_I and Clk_Q output by the phase interpolator I, Q, and compares the phase relationship between the input data and Clk_Q to generate the first lead signal UP and the second lag signal DN; The first lead signal UP and the second...
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Abstract
The invention discloses a half-rate clock data recovery circuit based on phase selection interpolation. The purpose is to solve the problem that the phase selection interpolation circuit for generating a pair of adjustable quadrature clock signals in the existing structure is too complicated, and proposes a A combination method of a novel phase-selective interpolation circuit. The half-rate clock data recovery circuit based on the phase selection / interpolation type includes a half-rate Bang-Bang type phase detector, a phase selector, a phase interpolator, a digital filter, a digital controller and an outer ring reference clock, and the phase selection Compared with the original structure, the interpolation circuit uses a group of phase selection circuits. While ensuring the generation of a pair of adjustable quadrature clock signals, the scale of the circuit is reduced, thereby reducing the area of the subsequent layout and reducing the power of the overall circuit. consumption.
Description
technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit design, relates to a clock data recovery circuit for high-speed serial communication, and specifically refers to a phase selection / interpolation-based half-rate clock data recovery circuit. Background technique [0002] The clock data recovery circuit is a key module to realize high-speed serial communication. In many transmission systems, the data stream does not have a clock signal associated with it, so the clock data recovery circuit needs to recover the clock signal from the received serial data, and retime the received data through the recovered clock, sampling Noise-containing data, thereby eliminating the jitter introduced during data transmission. [0003] The traditional half-rate clock data recovery circuit structure based on phase selection / interpolation is as follows: figure 1 shown. The circuit consists of half-rate Bang-Bang phase detector, digital filter...
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