39results about How to "Less control signal" patented technology

This invention relates to one double voltage line nanometer piezoelectricity driver, its control method and controller, which is characterized by the following parts: left and right piezoelectricity drivers are connected by mechanic series to form two connectors independently and controllable with middle, left and right areas; the base sliding along shape direction matching with two connector is set vertical to the connectors and the three areas separately form friction force.

The invention provides a method and a system for making a resource plan for a downlink-aided datum signal in the multi-carrier wideband system. The system consists of a base station, user equipment and a transmission program manager. The base station transmits a downlink datum signal. The user equipment receives the downlink datum signal and obtains at least one channel state message with usable frequency band from the downlink datum signal which is used in the next downlink frequency band. The transmission program manager is coupled with the base station and distributes the wireless resources to the user equipment according to the channel state fed back by the user equipment. The feedback of the channel state is at least partially based on the channel state information.

The invention discloses a driving method and a driving circuit of a liquid crystal panel and a liquid crystal display device. The driving method of the liquid crystal panel comprises a scanning driving process and a data driving process, wherein an overlap region is formed in the middle of switching from driving of an upper row of scan line to driving of a lower row of scan line; and the data diving process comprises a step of outputting a data signal corresponding to the lower row of data line after the data signal corresponding to the upper row of scan line continues to the overlap region. According to the driving method, the wiring of the liquid crystal panel is reduced, the corresponding control signals are reduced, the design difficulty is reduced, and the specification of a required control chip is correspondingly reduced to fulfill the aim of reducing the cost.

When chip is in stand by mode, system operation timer of the chip is closed so that each module in the chip stops working. Control is started up under slow timer to maintain save mode so as to reach purpose of reducing power consumption and saving electricity. In order to keep synchronization to base station when save mode exits, the invention designs a calculation method to keep good synchronization to base station when save mode exits, and to possess very small frequency deviation. Comparing with prior art, the invention possesses advantages of few control signals, easy of implementation, controllable time in save mode, and small frequency deviation.

In a method of selecting one or more transponders, the time duration of a reference interval is transmitted by the base station to the transponders in the header section of an information packet, each transponder compares the respective time durations of the reference interval and of a first time interval, and the further selection of the transponder depends on the result of the comparison.

In an imaging device including imaging elements, a driver configuration which does not require much layout space and ensures a reduced number of wirings is provided. The imaging device includes imaging elements 1 arranged in a matrix or in lines and a single driver circuit 6 disposed along the vertical direction of the matrix or along the direction in which the lines extend to control the driving of the imaging elements 1. Then, the driver circuit 6 serves the double function of a reset driver adapted to reset the imaging elements and a read driver adapted to read out the signals from the imaging elements.

In an imaging device including imaging elements, a driver configuration which does not require much layout space and ensures a reduced number of wirings is provided. The imaging device includes imaging elements 1 arranged in a matrix or in lines and a single driver circuit 6 disposed along the vertical direction of the matrix or along the direction in which the lines extend to control the driving of the imaging elements 1. Then, the driver circuit 6 serves the double function of a reset driver adapted to reset the imaging elements and a read driver adapted to read out the signals from the imaging elements.

The invention discloses an RRAM voltage generating system. The RRAM voltage generating system comprises an electric charge pump, a square-wave oscillator, a linear voltage stabilizer, an electrifying control circuit and a voltage and current reference source, wherein the electric charge pump is used for rising the voltage of an external power supply and providing power for other sub circuits; the square-wave oscillator is used for providing a clock signal; an output end of the square-wave oscillator is connected with a clock signal input end of the electric charge pump; the linear voltage stabilizer is used for providing driving voltage for the operation of a storage unit, and an output end of the linear voltage stabilizer is sequentially connected with a row and column decoder and a storage unit array; the linear voltage stabilizer is synchronously connected with an external power supply VCC and an electric charge pump output power supply VPP for supplying power; the electrifying control circuit is used for providing an electrifying reset signal for the system and meanwhile controlling the ordered start of the electric charge pump, the square-wave oscillator and the linear voltage stabilizer; the voltage and current reference source is used for providing reference voltage and reference current for the electric charge pump, the square-wave oscillator, the linear voltage stabilizer and the electrifying control circuit. An external power supply and the electric charge pump of a double-branch structure with good technological compatibility are adopted for supplying power respectively for the linear voltage stabilizer, and support multiple bites.

The invention discloses a CMOS fully digital BPSK modulation pulse radio ultra-wideband transmitter, which includes a BPSK modulation module, a time-delay generation module, a pulse sequence generation module and an antenna. The BPSK modulation module processes an input digital signal DATA and a clock signal CLK, and generates a digital signal that meets BPSK modulation requirements. Each time-delay generation circuit of the time-delay generation module delays a modulation signal output from the BPSK modulation module on the basis of the time-delay characteristics of an inverter and then obtains different time delay outputs, and is used for controlling a corresponding pulse sequence generation circuit so that the pulse sequence generation circuit generates a pulse unit identical in time width. Each pulse sequence generation circuit of the pulse sequence generation module generates a monopulse signal, and all pulse signals are combined to form a pulse sequence, which is output by serving as an output signal and emitted by the antenna. Wireless emission signals generated by the transmitter meet the requirements of the frequency spectrum and the work frequency range of UWB.

The invention provides a pixel driving circuit and a driving method thereof and a display device, relates to the technical field of display, and aims to solve the problems that a pixel driving circuitis complex in control signal and poor in display brightness uniformity of the display device due to threshold voltage drift. In the pixel driving circuit, a first end of a first storage sub-circuit is connected with a control end; the power supply control sub-circuit is connected with the light-emitting control signal line, the first power line and the first end of the driving sub-circuit; the compensation sub-circuit is connected with the first grid line, the control end of the driving sub-circuit and the first end of the driving sub-circuit; the data writing sub-circuit is connected with the second end of the first storage sub-circuit; and the first reset sub-circuit is connected with the reset signal line, the first power line and the control end of the drive sub-circuit. The first control sub-circuit is connected with the first grid line, the initialization signal line and the second end of the driving sub-circuit. The pixel driving circuit provided by the invention is used for driving the light-emitting element to emit light.

The invention relates to a flash lamp control circuit, which can control the illumination according to the sensitive voltage and preset voltage. Said control circuit is formed by the first comparer, the second comparer and a logic gate; or formed by a comparer, the first reverse device, the first crystal tube, the first logic gate and the second logic gate. The invention can instantly discharge the capacitor without additional control signal when the trigger signal is stopped. And it can also comprise a clamp circuit, which can clamp the sensitive voltage lower than preset voltage according to a full-flash signal.

The dual piezoelectric linear nano-positioning piezoelectric actuator, its control method and controller are characterized in that the left and right piezoelectric actuators are fixedly connected in mechanical series along the deformation direction to form an independently controllable duplex; The conjoined body is divided into a middle area, a left area and a right area along its deformation direction, and a base body which slides and fits with the two conjoined bodies in its deformation direction is set, and the two conjoined bodies are arranged or fixed on the other side perpendicular to the deformation direction of the two conjoined bodies. The positive pressure of the force-bearing pad on the top and the base body forms friction forces in the three areas of the base body and the two conjoined bodies, and the maximum static friction force of any one area is not greater than the sum of the maximum static friction forces of the other two areas. The invention only needs two piezoelectric actuators, integrated structure, easy miniaturization and integration, two-way controllable walking, large thrust, large working temperature range, large stroke, high precision, and is also suitable for ultra-low temperature, ultra-high vacuum , strong magnetic field and other extreme physical environments.

The invention relates to an integrated comprehensive power distribution measurement and control device. The measurement and control device comprises a box body (1). A display screen (2), buttons (3) and an indicating lamp (4) are arranged on a front panel of the box body (1). A power supply (5) and a plurality of plugging ports (6) are arranged on a rear panel of the box body (1). A functional module (7) is plugged in each plugging port (6). A central host is arranged in the box body (1). The display screen (2), the buttons (3) and the indicating lamp (4) are connected with the central host. The power supply (5) supplies power for the whole comprehensive power distribution measurement and control device. The functional modules (7) are and connected with the central host through plugging into the plugging ports (6). The device solves the problems that power monitoring devices on the market are different in size and are various in kind, wiring is complex, and functions are repeated. In addition, stability and reliability of electric cabinet system working are raised.

The embodiment of the invention discloses a power management circuit and a control method and system thereof. The power management circuit comprises a first power management chip and a reserved resistor position, wherein the first power management chip comprises a state machine module, a first control pin and a first power pin, and two ends of the reserved resistor position are respectively connected with the first control pin and the first power pin; the state machine module is used for triggering a power-on function or a reset function of the first power management chip through the first control pin under the condition that a first resistor is mounted at the reserved resistor position; or is used for triggering the power-on function or the reset function of the first power management chip through an external control module and the first control pin under the condition that the first resistor is not mounted at the reserved resistor position. Due to the fact that three pins in the first power management chip are combined into one control pin, the chip area is reduced, and the manufacturing cost is saved; and moreover, the risk that key signals are interfered is reduced, and the system stability is improved.

The invention discloses an SRAM (Static Random Access Memory) storage unit and a memory, relates to the technical field of circuit design, and is used for improving data security and reducing the area and power consumption of the SRAM. The SRAM storage unit comprises a data latch circuit, a first switching circuit, a second switching circuit, a third switching circuit and a storage circuit. The data latch circuit is provided with a first output end, a second output end and a conversion node. The first switching circuit is connected in series between the second output end and the conversion node. The second switch circuit is connected in series between the first output end and the first end of the storage circuit. The third switching circuit is connected in series between the conversion node and the first end of the storage circuit. The second end of the storage circuit is used for being electrically connected with a grounding end. The SRAM memory comprises the SRAM memory cell provided by the technical scheme.

The present invention provides a control circuit, including a current source module, a conversion module and a first comparison module: the current source module is used to generate a current signal whose magnitude is positively correlated with temperature; the conversion module includes a first conversion unit and / or a second conversion unit , the first conversion unit is used to provide the first voltage signal to the positive input terminal of the first comparison module, and the first voltage signal is positively correlated with the magnitude of the current signal generated by the current source module; the second conversion unit is used to provide the first comparison module The reverse input terminal of the module provides a second voltage signal, and the second voltage signal is negatively correlated with the magnitude of the current signal generated by the current source module; the first comparison module is used to output control when the positive input terminal is greater than the voltage signal of the reverse input terminal signal, the control signal is negatively correlated with the voltage signal difference between the positive input terminal and the negative input terminal of the first comparison module. Correspondingly, the invention also provides a backlight driving device and a display device, and the invention can prevent the temperature of the display device from being too high.

When chip is in stand by mode, system operation timer of the chip is closed so that each module in the chip stops working. Control is started up under slow timer to maintain save mode so as to reach purpose of reducing power consumption and saving electricity. In order to keep synchronization to base station when save mode exits, the invention designs a calculation method to keep good synchronization to base station when save mode exits, and to possess very small frequency deviation. Comparing with prior art, the invention possesses advantages of few control signals, easy of implementation, controllable time in save mode, and small frequency deviation.

A drive method and drive circuit for a liquid crystal panel and a liquid crystal display device. The drive method for a liquid crystal panel includes a scan drive process and a data drive process. In the scan drive process, an overlap region turned on at the same time is formed in the middle of switching drive of a previous row of scan line to drive of a next row of scan line. In the data drive process, after a data signal corresponding to the previous row of scan line is sustained to the end of the overlap region, a data signal corresponding to the next row of scan line is output.

The invention discloses a time-analog switching circuit and a single photon flight time measuring method. The time-analog switching circuit comprises a signal input logic unit, a timing unit, a voltage holding unit and a read out unit; the signal input logic unit converts a photon signal into a logic electrical level, and the input end of the signal input logic unit correspondingly receives the photon signal, a start signal and a stop signal, and the output end of the signal input logic unit is connected with the input end of the timing unit; the timing unit includes a current mirror structureproviding a stable charging current, a current mirror structure providing a current source and a timing capacitor, and a voltage of an electrode plate of the timing capacitor linearly increases withtime after the timing capacitor starts counting; the voltage holding unit is used for holding the voltage of the electrode plate of the timing capacitor, the input end of the voltage holding unit is connected with the output end of the timing unit, the output end of the voltage holding unit is connected with the read out unit, and the read out unit reads out a voltage signal of the electrode plate. According to the time-analog switching circuit and the single photon flight time measuring method, the manufacturing process is compatible with the CMOS process, the manufacturing cost is low, and the rate of finished products is high; and meanwhile, the time-analog switching circuit has the advantages of high filling factors, high resolution and a large measuring range.

The invention discloses a melon and fruit picking device and a picking method thereof, which relate to the technical field of agricultural equipment. The melon and fruit picking device comprises a clamping device, a cutting device and a control device, wherein the clamping device comprises a step motor, a driven gear, a left support swinging rod, a left finger, a driving gear, a right support swinging rod, a right finger and supporting blocks, the supporting blocks are arranged under the left finger and the right finger, the driving gear and the step motor are connected, the driving gear and the driven gear are connected through a gear pair, the left finger is arranged at the end parts of the left support swinging rod and the driven gear, the right finger is arranged at the end parts of the right support swinging rod and the driving gear, the cutting device comprises a cutter, a swinging air cylinder and an electromagnetic reversing valve, the cutter is arranged on an output shaft of the swinging air cylinder, the electromagnetic reversing valve is arranged on the swinging air cylinder, the swinging air cylinder is arranged on a cutter frame, and the cutter frame is arranged on a back seat vertically and fixedly arranged on a base. The melon and fruit picking device and the method can be used for automatically picking melons and fruits, and a large amount of time and labor canbe saved for laborers.

The present disclosure relates to a differential input circuit, an amplifying circuit, and a display device. The differential input circuit includes: a first power supply module, a second power supply module, a first shunt module, a second shunt module, a first output module and a second Output module: control the first power module to output the first signal, the second signal and the third signal through the first bias signal, the second power module receives the first signal, and outputs the fourth signal and the fifth signal, through the differential input signal Control the first shunt module, the second shunt module, the first output module and the second output module, so that when the differential input signal changes, the transconductance of the differential input circuit is constant, and because the first shunt module, the second shunt module, the second Both the first output module and the second output module are controlled by differential input signals, and the number of control signals is small, so that the circuit control is simple and easy to realize, the manufacturing process is simplified, and the cost is saved.

The invention discloses an X-shaped ferroelectric memory array structure which belongs to the integrated circuit design manufacturing technical field. The array structure of the invention takes X-shaped ferroelectric memory cells as basic components, wherein, each ferroelectric memory cell respectively shares a control line CL with memory cells in the same row or the same column in the horizontal-vertical direction; the memory cells in the same column shares a data signal line BL in the column direction; the memory cells in the same row shares a BL in the row direction; rows and columns do notshare BLs. The X-shaped ferroelectric memory array structure is based on a data storage and read-write mechanism of a ferroelectric memory and borrows ideas from partial principles and read-write means of an FeRAM incorporated PL array architecture, thereby control and data read-write of the memory cells can be simultaneously performed along the row direction and the column direction and parallelread-write of multi-bit data can be easily realized; the symmetry of circuits and the arrangement of peripheral circuits are optimized; the number and the scale of decoding and drive circuits are reduced; moreover, the length of the BL line can be reduced and then the read-write speed is improved.

The invention provides a two-wire multiplexing circuit, which relates to the technical field of communication circuits. It includes a magnetic coupling isolation circuit, a first communication circuit and a second communication circuit, the output end of the magnetic coupling isolation circuit is connected to the input end of the first communication circuit, and the output end of the first communication circuit is connected to the input end of the second communication circuit. There is no need to send or receive control conversion signal lines, which saves output or input interfaces, saves costs, and improves data transmission efficiency.

The invention discloses an SRAM storage unit and a memory, relates to the technical field of circuit design, and is used for improving data security and reducing the area and power consumption of the SRAM memory. The SRAM storage unit includes: a data latch circuit, a first switch circuit, a second switch circuit, a third switch circuit and a storage circuit. The data latch circuit has a first output terminal, a second output terminal and a switching node. The first switch circuit is connected in series between the second output terminal and the conversion node. The second switch circuit is connected in series between the first output terminal and the first terminal of the storage circuit. The third switch circuit is connected in series between the conversion node and the first terminal of the storage circuit. The second end of the storage circuit is electrically connected to the ground end. The SRAM memory includes the SRAM storage unit mentioned in the above technical solution.

The invention relates to a method of implementing the compatibility of address multiplexing logic with SDRAM by, using a processor to send control word to the address multiplexing logic so as to make the address multiplexing compatible with the SDRAMs of various driving modes, and it includes: the processor selects the sequence code of control word according to the driving mode of SDRAM, and the selected sequence code corresponds to the current driving mode of SDRAM; under the synchronous control of a clock signal, the processor writes the sequence code in address multiplexing logic unit; the logic unit judges if the received sequence code matches with the desired value of sequence code: if it does, select the corresponding driving mode of SDRAM to the desired value and make line and column address multiplexing processing on the linear address outputted by the processor; otherwise, keep the original driving mode of SDRAM, such as a default driving mode. Both the clock signal and sequence code signal are led through a universal pin on the processor to the address multiplexing logic unit. It can be applied in any circumference of using processors and memories.

The invention discloses a CMOS full-digital BPSK modulation pulse radio ultra-wideband transmitter, which is composed of a BPSK modulation module, a delay generation module, a pulse sequence generation module and an antenna; the BPSK modulation module processes the input digital signal DATA and the clock signal CLK, Generate a digital signal that meets the requirements of BPSK modulation; the delay generation circuit of each stage of the delay generation module uses the characteristics of inverter delay to delay the modulated signal output by the BPSK modulation module to obtain different delay outputs, which are used to control the corresponding The pulse sequence generating circuit of the device generates a pulse unit of equal time width; each stage of the pulse sequence generating circuit of the pulse sequence generating module generates a single pulse signal, and all the pulse signals are combined into a pulse sequence as the output signal output via the antenna. The wireless transmission signal generated by the invention meets the requirements of the frequency spectrum and working frequency band of UWB.

The multi-way reversing valve comprises an oil inlet unit and an oil return unit, a plurality of working units are connected between the oil inlet unit and the oil return unit in series, the oil inlet unit comprises an oil inlet valve body and a main oil inlet formed in the oil inlet valve body, the oil return unit comprises an oil return valve body and a main oil return opening formed in the oil return valve body, and each working unit comprises a working valve body. And a valve core is arranged in the working valve body. In the using process, the corresponding number of working units can be arranged according to the number of executive components and requirements, universality is high, and the working valve body is simple in structure, quite convenient to machine and low in manufacturing cost. When the valve element is in the neutral position state, the multi-way reversing valve is in the unloading state, an electromagnetic unloading valve does not need to be additionally arranged, the structure is simplified, control signals are reduced, and control of an upper computer is simpler; and the sandwich valve can be directly added on the working valve body, and a non-standard oil path block or a matched valve does not need to be developed, so that the universality is high.

The invention discloses a compact type time to analog conversion circuit applied to a single-photon detector. The compact type time to analog conversion circuit applied to the single-photon detector comprises an RS trigger, a timing capacitor C and eight MOS transistors, wherein the MP0 and the MP1 form a differential structure as an input stage; the MN1 and the MP1 form a complementary CMOS switch; the three MOS transistors including the MP0, the MN1 and the MP1 form a control logic together, so that discharging of the timing capacitor C is controlled; the MP2 and the MP3 are used as two PMOSswitches used for controlling the reset operation of the timing capacitor C; and the MN2 and the MN3 form a source-level follower used for reading voltage on the timing capacitor C. The compact typetime to analog conversion circuit applied to the single-photon detector in the invention is small in capacitance area, small in transistor number and simple in structure; the effect of greatly reducing the area of a circuit layout is achieved; the circuit density and integrity are improved; fill factors of picture elements are effectively increased; simultaneously, the overall power consumption ofthe circuit is also reduced; the manufacture cost is low; the performance consistence of various circuits is good; and the yield is high.

The invention relates to a flash lamp control circuit, which can control the illumination according to the sensitive voltage and preset voltage. Said control circuit is formed by the first comparer, the second comparer and a logic gate; or formed by a comparer, the first reverse device, the first crystal tube, the first logic gate and the second logic gate. The invention can instantly discharge the capacitor without additional control signal when the trigger signal is stopped. And it can also comprise a clamp circuit, which can clamp the sensitive voltage lower than preset voltage according toa full-flash signal.