39results about How to "Less control signal" patented technology

This invention relates to one double voltage line nanometer piezoelectricity driver, its control method and controller, which is characterized by the following parts: left and right piezoelectricity drivers are connected by mechanic series to form two connectors independently and controllable with middle, left and right areas; the base sliding along shape direction matching with two connector is set vertical to the connectors and the three areas separately form friction force.

The invention provides a method and a system for making a resource plan for a downlink-aided datum signal in the multi-carrier wideband system. The system consists of a base station, user equipment and a transmission program manager. The base station transmits a downlink datum signal. The user equipment receives the downlink datum signal and obtains at least one channel state message with usable frequency band from the downlink datum signal which is used in the next downlink frequency band. The transmission program manager is coupled with the base station and distributes the wireless resources to the user equipment according to the channel state fed back by the user equipment. The feedback of the channel state is at least partially based on the channel state information.

The invention discloses a driving method and a driving circuit of a liquid crystal panel and a liquid crystal display device. The driving method of the liquid crystal panel comprises a scanning driving process and a data driving process, wherein an overlap region is formed in the middle of switching from driving of an upper row of scan line to driving of a lower row of scan line; and the data diving process comprises a step of outputting a data signal corresponding to the lower row of data line after the data signal corresponding to the upper row of scan line continues to the overlap region. According to the driving method, the wiring of the liquid crystal panel is reduced, the corresponding control signals are reduced, the design difficulty is reduced, and the specification of a required control chip is correspondingly reduced to fulfill the aim of reducing the cost.

When chip is in stand by mode, system operation timer of the chip is closed so that each module in the chip stops working. Control is started up under slow timer to maintain save mode so as to reach purpose of reducing power consumption and saving electricity. In order to keep synchronization to base station when save mode exits, the invention designs a calculation method to keep good synchronization to base station when save mode exits, and to possess very small frequency deviation. Comparing with prior art, the invention possesses advantages of few control signals, easy of implementation, controllable time in save mode, and small frequency deviation.

In a method of selecting one or more transponders, the time duration of a reference interval is transmitted by the base station to the transponders in the header section of an information packet, each transponder compares the respective time durations of the reference interval and of a first time interval, and the further selection of the transponder depends on the result of the comparison.

In an imaging device including imaging elements, a driver configuration which does not require much layout space and ensures a reduced number of wirings is provided. The imaging device includes imaging elements 1 arranged in a matrix or in lines and a single driver circuit 6 disposed along the vertical direction of the matrix or along the direction in which the lines extend to control the driving of the imaging elements 1. Then, the driver circuit 6 serves the double function of a reset driver adapted to reset the imaging elements and a read driver adapted to read out the signals from the imaging elements.

The invention discloses an RRAM voltage generating system. The RRAM voltage generating system comprises an electric charge pump, a square-wave oscillator, a linear voltage stabilizer, an electrifying control circuit and a voltage and current reference source, wherein the electric charge pump is used for rising the voltage of an external power supply and providing power for other sub circuits; the square-wave oscillator is used for providing a clock signal; an output end of the square-wave oscillator is connected with a clock signal input end of the electric charge pump; the linear voltage stabilizer is used for providing driving voltage for the operation of a storage unit, and an output end of the linear voltage stabilizer is sequentially connected with a row and column decoder and a storage unit array; the linear voltage stabilizer is synchronously connected with an external power supply VCC and an electric charge pump output power supply VPP for supplying power; the electrifying control circuit is used for providing an electrifying reset signal for the system and meanwhile controlling the ordered start of the electric charge pump, the square-wave oscillator and the linear voltage stabilizer; the voltage and current reference source is used for providing reference voltage and reference current for the electric charge pump, the square-wave oscillator, the linear voltage stabilizer and the electrifying control circuit. An external power supply and the electric charge pump of a double-branch structure with good technological compatibility are adopted for supplying power respectively for the linear voltage stabilizer, and support multiple bites.

The invention discloses a CMOS fully digital BPSK modulation pulse radio ultra-wideband transmitter, which includes a BPSK modulation module, a time-delay generation module, a pulse sequence generation module and an antenna. The BPSK modulation module processes an input digital signal DATA and a clock signal CLK, and generates a digital signal that meets BPSK modulation requirements. Each time-delay generation circuit of the time-delay generation module delays a modulation signal output from the BPSK modulation module on the basis of the time-delay characteristics of an inverter and then obtains different time delay outputs, and is used for controlling a corresponding pulse sequence generation circuit so that the pulse sequence generation circuit generates a pulse unit identical in time width. Each pulse sequence generation circuit of the pulse sequence generation module generates a monopulse signal, and all pulse signals are combined to form a pulse sequence, which is output by serving as an output signal and emitted by the antenna. Wireless emission signals generated by the transmitter meet the requirements of the frequency spectrum and the work frequency range of UWB.

The invention provides a pixel driving circuit and a driving method thereof and a display device, relates to the technical field of display, and aims to solve the problems that a pixel driving circuitis complex in control signal and poor in display brightness uniformity of the display device due to threshold voltage drift. In the pixel driving circuit, a first end of a first storage sub-circuit is connected with a control end; the power supply control sub-circuit is connected with the light-emitting control signal line, the first power line and the first end of the driving sub-circuit; the compensation sub-circuit is connected with the first grid line, the control end of the driving sub-circuit and the first end of the driving sub-circuit; the data writing sub-circuit is connected with the second end of the first storage sub-circuit; and the first reset sub-circuit is connected with the reset signal line, the first power line and the control end of the drive sub-circuit. The first control sub-circuit is connected with the first grid line, the initialization signal line and the second end of the driving sub-circuit. The pixel driving circuit provided by the invention is used for driving the light-emitting element to emit light.

The embodiment of the invention discloses a power management circuit and a control method and system thereof. The power management circuit comprises a first power management chip and a reserved resistor position, wherein the first power management chip comprises a state machine module, a first control pin and a first power pin, and two ends of the reserved resistor position are respectively connected with the first control pin and the first power pin; the state machine module is used for triggering a power-on function or a reset function of the first power management chip through the first control pin under the condition that a first resistor is mounted at the reserved resistor position; or is used for triggering the power-on function or the reset function of the first power management chip through an external control module and the first control pin under the condition that the first resistor is not mounted at the reserved resistor position. Due to the fact that three pins in the first power management chip are combined into one control pin, the chip area is reduced, and the manufacturing cost is saved; and moreover, the risk that key signals are interfered is reduced, and the system stability is improved.

The invention discloses an SRAM (Static Random Access Memory) storage unit and a memory, relates to the technical field of circuit design, and is used for improving data security and reducing the area and power consumption of the SRAM. The SRAM storage unit comprises a data latch circuit, a first switching circuit, a second switching circuit, a third switching circuit and a storage circuit. The data latch circuit is provided with a first output end, a second output end and a conversion node. The first switching circuit is connected in series between the second output end and the conversion node. The second switch circuit is connected in series between the first output end and the first end of the storage circuit. The third switching circuit is connected in series between the conversion node and the first end of the storage circuit. The second end of the storage circuit is used for being electrically connected with a grounding end. The SRAM memory comprises the SRAM memory cell provided by the technical scheme.

The invention relates to a method of implementing the compatibility of address multiplexing logic with SDRAM by, using a processor to send control word to the address multiplexing logic so as to make the address multiplexing compatible with the SDRAMs of various driving modes, and it includes: the processor selects the sequence code of control word according to the driving mode of SDRAM, and the selected sequence code corresponds to the current driving mode of SDRAM; under the synchronous control of a clock signal, the processor writes the sequence code in address multiplexing logic unit; the logic unit judges if the received sequence code matches with the desired value of sequence code: if it does, select the corresponding driving mode of SDRAM to the desired value and make line and column address multiplexing processing on the linear address outputted by the processor; otherwise, keep the original driving mode of SDRAM, such as a default driving mode. Both the clock signal and sequence code signal are led through a universal pin on the processor to the address multiplexing logic unit. It can be applied in any circumference of using processors and memories.