Address multiplexing logic implementation method with SDRAM compatible

Abstract

The invention relates to a method of implementing the compatibility of address multiplexing logic with SDRAM by, using a processor to send control word to the address multiplexing logic so as to make the address multiplexing compatible with the SDRAMs of various driving modes, and it includes: the processor selects the sequence code of control word according to the driving mode of SDRAM, and the selected sequence code corresponds to the current driving mode of SDRAM; under the synchronous control of a clock signal, the processor writes the sequence code in address multiplexing logic unit; the logic unit judges if the received sequence code matches with the desired value of sequence code: if it does, select the corresponding driving mode of SDRAM to the desired value and make line and column address multiplexing processing on the linear address outputted by the processor; otherwise, keep the original driving mode of SDRAM, such as a default driving mode. Both the clock signal and sequence code signal are led through a universal pin on the processor to the address multiplexing logic unit. It can be applied in any circumference of using processors and memories.

Description

technical field [0001] The present invention relates to an application technology of SDRAM, more precisely, it relates to the technology of realizing compatibility between address multiplexing logic and SDRAM, which can be applied to any occasion using processor and memory, such as communication, computer, artificial intelligence, instrumentation, etc. . Background technique [0002] In some cases, the address sent by the SDRAM controller of the processor is a linear address, but the address required by SDRAM and memory sticks using SDRAM is a row and column multiplexed address. In order for the processor to access SDRAM, it must An address multiplexing logic is added between the processor and SDRAM. This address multiplexing logic performs row and column multiplexing on the linear address sent by the processor, and then sends the multiplexed row and column addresses to SDRAM or SDRAM memory. The connection relationship between the processor and SDRAM is shown in Figure 1. ...

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Problems solved by technology

[0008] Comparing the above two driving methods, it is found that although the column address of the latter is only increased by one bit, the information of each bit of the linear address of the processor has changed greatly as a result. Therefore, it is necessary to make the same printed circuit board (PCB) design. Compatible with SDRAMs of different capacities, the multiplexing method of the address multiplexing logic unit must be able to be flexibly modified through software settings

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