359results about How to "Reduce selection requirements" patented technology

A write bit line and a read bit line are provided separately for a memory cell. A source line connecting to the memory cell is formed of a source impurity region the same in conductivity type as a substrate region. A memory cell transistor and the source impurity region are connected by a metal interconnection line of a low resistance. A rise in the source line potential can be prevented, and a memory cell current can reliably be generated according to storage data. Further, fast data reading can be achieved. Additionally, by performing precharging and data amplification in a unit of read bit line, the load of the read bit line can be alleviated to achieve fast reading. An accessing time of a non-volatile semiconductor memory device that uses a variable resistance element as a storage element is reduced without increasing the current consumption.

A “Spatial Navigator” provides a document navigation environment that leverages user spatial memory. Graphical thumbnail-type representations (“thumbnails”) provide scaled versions of entire documents. Changes to documents are immediately reflected in corresponding thumbnails. Similarly, document search results are highlighted in corresponding thumbnails. One or more dynamic document selection windows present arrangements of a plurality of these thumbnails for user selection and interaction. Each dynamic document selection window provides real-time inter-file navigation by allowing user selection and opening of documents, or any location or portion of a document, through user interaction with the corresponding thumbnail. Once a document is opened, intra-file navigation is enhanced by providing another scaled version of the entire document in a dynamic scrollbar adjacent to a primary document editing / viewing window. Selection of any point within this scrollbar-based thumbnail causes an immediate jump to the corresponding document location in the primary document editing / viewing window.

A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time τMV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time τMV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.