System and method for executing scan test

Abstract

A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.

Description

technical field [0001] The present invention relates generally to scan testing and memory built-in self-test (BIST) of integrated circuits and, more particularly, to systems and methods for performing scan testing and memory BIST testing on integrated circuits using scan bypass and BIST bypass. Background technique [0002] In recent years, there has been tremendous development in the fields of semiconductor devices and electronic circuit integration. Recently, a single system-on-chip (SoC) with multiple packaging types or packaging options is available. In small package embodiments, certain functional intellectual property (IP) blocks may be masked out, depending on the package type selected. These masked IP blocks may include combinational logic blocks and memory blocks. [0003] FIG. 1 illustrates a schematic diagram of a scan test using a scan chain design and a memory test using a BIST controller in a system including a scan test system and a BIST test system. That i...

AI Technical Summary

Problems solved by technology

However, IC10 may still be usable for other package types where the covered block is not necessary for kinetic operation

Therefore, full-scan testing and full-memory BIST testing can lead to unintentional yield loss

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