Method for reducing arc defects on semiconductor wafer surface

Abstract

The invention provides a method for reducing the surface electric arcing defect of a semiconductor chip. The method at least comprises the steps that a semiconductor chip element is etched to form a through hole; conducting layers are formed in the semiconductor chip and the through hole; the conducting layers are ground by means of a chemical mechanical grinding method of ground pulp; deionized water is adopted for cleaning a semiconductor. The semiconductor is cleaned through the deionized water after CMP, the electric arcing defect can be reduced or avoided, meanwhile particle pollution caused by the residual ground pulp is reduced, processing failure of the element is avoided, and the yield is improved.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, in particular to a method for reducing arc defects on the surface of a semiconductor wafer. Background technique [0002] With the advent of the era of ultra-large volume circuits, the size of semiconductor components is shrinking, and the intervals between circuits in semiconductor components are getting smaller and smaller, and the alignment work required between various processes will become more important. Therefore, for manufacturers, how to avoid the contamination of semiconductor elements by particles in the manufacturing process when the size of semiconductor elements is reduced, and because the particles in the manufacturing process remain in the alignment keys, resulting in incorrect alignment between processes, will follow As the size of semiconductor elements decreases, the requirements become increasingly stringent. [0003] In ultra-large volume circuits, high temperature...

AI Technical Summary

Problems solved by technology

If the line width is less than 0.5μm, the same particles will have a greater impact

Images