Stress-aware design for integrated circuits

Abstract

A method of circuit design involving an integrated circuit (IC) having an interposer may include identifying active resources in regions (465, 470, 470, 465, 470, 535) implemented within said IC (200, 500), said amount of stress exceeds a normalized amount of stress on said interposer; and according to said circuit design as implemented within said IC A stress-aware analysis selectively assigns elements of the circuit design to be implemented within the IC to the active resources. Another region (620) is characterized by a substantially normalized stress throughout the other regions.

Description

technical field [0001] One or more embodiments disclosed within this specification relate to integrated circuits (ICs). More specifically, one or more embodiments relate to stress-aware design for ICs and stress-aware implementation of circuit designs within ICs. Background technique [0002] Circuit designs continue to get larger, requiring larger integrated circuits (ICs) for implementation. In some cases, circuit designs that may be implemented using a single larger die may be implemented using an IC that includes two or more smaller dies. ICs that include two or more smaller dies may be referred to as "multi-die ICs." A multi-die IC is generally characterized as including two or more die coupled to each other and placed within a single IC package. Circuit designs are implemented across multiple dies rather than using a single larger die. [0003] Multi-die ICs often include physical characteristics that are not present in their single-die IC counterparts. For exampl...

AI Technical Summary

Problems solved by technology

Stresses typically greater than normalized stresses present within the die of conventional single die ICs can adversely affect the performance of active devices implemented within multi-die ICs

Images