Manufacturing method of power mosfet chip protection structure
A technology of protective structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems affecting the performance of chip protection structure, incomplete oxidation of silicon lines, and uneven thickness of silicon lines, so as to facilitate production Effects of control, guaranteed performance, and increased process tolerance
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0051] A method for manufacturing a power MOSFET chip protection structure, comprising the following steps:
[0052] 1. Growing the first layer of silicon dioxide 11 on the silicon wafer 10, preferably, the thickness of the first layer of silicon dioxide 11 is 400 angstroms;
[0053] Two. grow a layer of silicon nitride 12 on the first layer of silicon dioxide 11, such as figure 2 As shown, preferably, the thickness of silicon nitride is 1500 angstroms;
[0054] 3. Carry out dry etching in the field oxygen region around the power MOSFET chip, and etch a groove 13 on the silicon wafer 10, such as image 3 As shown, preferably, the depth h of the groove 13 is 5000 Angstroms;
[0055] Four. Deposit the second layer of silicon dioxide 14 at room temperature on the silicon wafer, such as Figure 4 As shown, preferably, the thickness of the second layer of silicon dioxide 14 is 6000 angstroms;
[0056] 5. Carry out photolithography and etching of the silicon line 15 structure a...
Embodiment 2
[0064] Based on Example 1, such as Figure 11 , Figure 11 shown as Figure 10 A partially enlarged view of the vertical intersection point A of the photoresist warp line Y and the photoresist weft line X of the grid-like lithographic pattern, the photoresist warp line Y includes the intersection area Y1 and the non-intersection area Y2, and the photoresist weft line X includes the intersection area X1 and the non-intersection area Y2. The intersection area X2, the length and line width of the intersection area Y1 of the photoresist meridian Y and the length and line width of the intersection area X1 of the photoresist weft X are respectively equal, and the line width of the non-intersection area Y2 of the photoresist warp Y is equal to that of the photoresist weft The line width of the non-intersection area X2 of X is equal, the line width of the intersection area Y1, X1 is smaller than the line width of the non-intersection area Y2, X2, the length of the intersection area Y...
Embodiment 3
[0067] Based on Example 2, such as Figure 11 , the intersecting area Y1 of photoresist warp Y includes central area Y11 and transition area Y12, the intersecting area X1 of photoresist weft X includes central area X11 and transition area X12, and the central point of central area Y11 (X11) is used as intersecting area Y1 (X1 ), the transition zone Y12 (X12) is located between the central zone Y11 (X11) and the non-crossing zone Y2 (X2), and the line width of the central zone Y11 (X11) is greater than the line width of the transition zone Y12 (X12).
[0068] Preferably, the length of the central area Y11 (X11) is equal to the line width of the central area Y11 (X11).
[0069] In the manufacturing method of the power MOSFET chip protection structure of the present invention, when the photolithography and etching of the silicon line structure are carried out at the bottom of the groove, the photolithographic pattern is grid-like, and the nodes (intersections) of the grid-like ph...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More