A Method for Generating Reachability Graph of Combinational Logic FPGA System Based on Petri Net

Abstract

The invention discloses a Petri-net-based combined logic FPGA (Field Programmable Gate Array) system reachability graph generation method. According to the Petri-net-based combined logic FPGA system reachability graph generation method, a combined logic FPGA system reachability graph is generated due to redefining of a transition motivation principle of a Petri net based on a Petri net modeling method of an combined logic FPGA system with stable gate circuit logical operation output which is corresponding to a circuit system under a stable input state serving as a research condition and a circuit logic function serving as a consideration object and state space of the FPGA system is clearly and completely displayed, so that the system can be detected whether a control objective violated state exists or not through traversal searching. The Petri-net-based combined logic FPGA system reachability graph generation method is a direct and forceful method for verifying logical errors of a VHDL (Vhsic Hardware Description Language) program and provides fundamental basis for formal verification of the VHDL program.

Description

technical field [0001] The invention relates to a method for generating reachable graphs of combinatorial logic FPGA systems based on Petri nets. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, Field Programmable Gate Array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It appeared as a semi-customized circuit in the field of application-specific integrated circuits (ASIC), which not only solved the shortcomings of custom circuits, but also overcome the shortcomings of the limited number of gate circuits of the original programmable device. FPGA uses a small look-up table (16×1RAM) to implement combinatorial logic, each look-up table is connected to the input of a D flip-flop, and the flip-flop drives other logic circuits or drives I / O, thus forming a combinatorial The logic function can also realize the basic logic unit module of the sequential logic function, and these modules are connecte...

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