A method of converting fpga hardware description language vhdl into common petri net

Abstract

The invention provides a method for converting filed programmable gate array (FPGA) Vhsic hardware description language (VHDL) to an ordinary Petri network. Aiming at a compiled VHDL program, the logic relationship between input and output is obtained, the logic relation between the input and the output is simplified to a virtual-to-physical (V2P) Boolean expression, the V2P Boolean expression is transformed, and then the transformed Boolean expression is utilized to be converted into the ordinary Petri network. A modeling method for the VHDL program is provided, and is a powerful tool for the simulation and the verification of the FPGA VHDL.

Description

technical field [0001] The invention relates to a method for converting FPGA hardware description language VHDL into common Petri net. Background technique [0002] FPGA (Field-ProgrammableGateArray) is a product further developed on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solved the shortcomings of the custom circuit, but also overcome the shortcomings of the limited number of gate circuits of the original programmable device. At present, the circuit design completed by hardware description language (VHDL) can be quickly burned to the FPGA for testing after simple synthesis and layout. The main application fields of FPGA (Field Programmable Logic Device) products are communications, consumer electronics, automotive electronics, industrial control, test and measurement, etc. With the increasing technical requirements, the scale and struc...

AI Technical Summary

Problems solved by technology

For example, in a railway traffic control system, the number of states of the system increases exponentially with the number of sensors and actuators. If a system has n sensors and actuators, the system states have 2 n , the number of states is very large, so FGPA faces the problem of high computational complexity

[0003] However, high computational complexity brings many practical problems, such as: VHDL program design and program debugging workload is cumbersome and huge, chip development cycle and cost cannot be adjusted; VHDL program simulation cannot verify each state (2 n ), the correctness and reliability of the program cannot be guaranteed, and program errors may cause serious accidents

Images