Photolithography marking and method applied to epitaxy process
A technology of lithography marking and epitaxial process, which is applied in the direction of photolithography exposure device, micro-lithography exposure equipment, electrical components, etc., can solve the problems of thick growth, poor quality, and inability to form lithography marks, etc., to achieve a solution effect of influence
Active Publication Date: 2017-02-15
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
At this time, because the silicon material still exists on the outer boundary and interface of the photolithography mark, when the epitaxial growth rate is fast, the growth thickness is thick, or the selection ratio is not high, the single crystal silicon grown from the silicon substrate will be directed towards the light. The engraved marking area is extended, resulting in lithographic markings that cannot be formed or poorly formed, resulting in inaccurate measurement results
[0006] In the traditional method, although the protective layer is used to reduce the impact of the epitaxial process on the lithographic mark, because the entire alignment mark still has a part in contact with silicon, and the protective material on the lithographic mark will still be covered by epitaxy as the process changes
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[0024] According to the photolithography mark applied in the epitaxial process of the present invention, the photolithography mark is placed in a dielectric material, and any outer boundary or outer interface is surrounded by a material that is difficult to grow by epitaxy.
[0025] Its implementation includes two parts, layout realization and process flow.
[0026] Its layout is realized as figure 2 Expressed. A base region of the dielectric layer is formed, which is realized through a photomask one. The formation of the photolithographic mark pattern is realized through the second mask, and the pattern includes two parts, the photolithographic mark area and the photolithographic mark itself. The photolithographic mark area is not a real pattern formed, but is only used to mark the area formed by the photolithographic mark to ensure that a forbidden area is formed between the photolithographic mark and the base area of the dielectric layer, and its size meets the require...
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The invention discloses a photoetching mark applying an epitaxial technology and a method thereof. The photoetching mark is put in a medium material, and any outer boundary or outer interface is surrounded by an epitaxial protecting layer which is hard to grow. The photoetching mark is thoroughly isolated from a silicon material, and the influence of epitaxial growth on the photoetching mark is thoroughly solved.
Description
technical field [0001] The invention relates to a semiconductor manufacturing method in the field of microelectronic chip manufacturing. Background technique [0002] The epitaxy process in semiconductor manufacturing is a common film-forming process. However, during epitaxial growth, graphic distortion is a relatively common phenomenon. The pattern distortion will affect the alignment accuracy of subsequent lithography, thereby restricting the overlay accuracy of lithography, and limiting the development and manufacture of small-sized epitaxial devices. How to avoid or reduce the amount of pattern distortion generated during epitaxial growth is very important for improving the precision of photolithography overlay. [0003] Common alignment marks before the epitaxial process are usually produced by directly etching the silicon substrate, so they are greatly affected by epitaxial distortion, so their alignment accuracy is usually relatively low. [0004] In order to solve...
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IPC IPC(8): H01L23/544H01L21/311G03F7/20
Inventor 王雷苏波李伟峰程晋广
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP