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Method and data processing device for cache block invalidation

A cache and cache line technology, applied in the direction of electrical digital data processing, memory system, memory architecture access/allocation, etc.

Active Publication Date: 2019-01-08
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This will then ensure that the CPU1 request will result in a cache miss and the correct data will be served from main memory

Method used

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  • Method and data processing device for cache block invalidation
  • Method and data processing device for cache block invalidation
  • Method and data processing device for cache block invalidation

Examples

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Embodiment Construction

[0014] figure 1 The organization of a typical digital signal processor system 100 to which the present invention is applicable (Prior Art) is described. The digital signal processor system 100 includes a central processing unit core 110 . The central processing unit core 110 contains the data processing portion of the digital signal processor system 100 . Central processing unit core 110 may be constructed as known in the art, and will typically include a register file, integer arithmetic logic unit, integer multiplier, and program flow control unit. Combination below Figures 2 to 4 An example of a suitable central processing unit core is described.

[0015] The digital signal processor system 100 includes several cache memories. figure 1 A pair of first level cache memories is illustrated. Level 1 instruction cache (L1I) 121 stores instructions used by central processing unit core 110 . The CPU core 110 first attempts to access any instruction from the L1 instruction...

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PUM

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Abstract

The present invention relates to a cache memory system and a method of performing block invalidation operations. The method of an embodiment aims to eliminate block invalidation operations in a multi-CPU environment by making the delay transparent to block invalidation operations by overlapping them with normal CPU accesses. A range check is performed on each CPU access while a block invalidation operation is in progress, and accesses within the address range mapped to the block invalidation operation are treated as cache misses to ensure that the requesting CPU will receive a valid data.

Description

technical field [0001] The technical field of the invention relates to cache memories for digital data processors. Background technique [0002] In a hierarchical cache system, a block invalidation operation may be required to invalidate a block of lines cached in the memory system. In a block coherent operation, the user programs the base address and number of words to be removed from the cache. The cache controller then iterates through the entire cache memory, and if the controller finds an address within a given address range, it marks the particular setting and mode as invalid (corresponding feature). Block invalidation operations are often required to maintain data coherency within multiprocessor systems. [0003] Figure 6 Examples are described in . In a multi-core environment, CPU1 601 is updating data in address range A. After CPU1 completes, other CPUs may begin process 603 and update data within the same address range. If CPU1 needs to access data in this ad...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0877G06F12/0893
CPCG06F12/0891Y02D10/00G06F12/122G06F12/08G06F13/28G06F12/0808G06F12/0811G06F2212/1021G06F2212/62
Inventor 纳韦恩·布霍里亚拉古拉姆·达莫达兰阿比吉特·阿肖克·查查德
Owner TEXAS INSTR INC