Onsite programmable gate array configuration method

Abstract

The invention discloses an onsite programmable gate array configuration method. An onsite programmable gate array comprises multiple logic modules, multiple wiring resources in an X-direction, multiple wiring resources in a Y-direction, an excitation signal input end and a response signal output end. Each logic module is composed of logic units and comprises a lower side input end, a lower side output end, a left side input end, a left side output end, an upper side input end, an upper side output end, a right side input end and a right side output end. A configuration mode of "four-in-four-out" is adopted by each logic module so that the input ends and the output ends of the logic modules are utilized to the largest limit and number of the required ports is greatly reduced, and thus the method is applicable to fault detection of connection between the logic modules and local interconnection resources in the onsite programmable gate array.

Description

Technical field [0001] The invention relates to the technical field of local interconnection resource failure detection of a field programmable gate array, in particular to a configuration method of a field programmable gate array. Background technique [0002] The user programmability and low development cost of field programmable gate array (FPGA) make it an important technology for realizing modern circuits and systems. Compared with Application Specific Integrated Circuits (ASIC), FPGA's low R&D cost and short development cycle make it an important core technology for modern digital circuits and systems, and its market share is increasing year by year. . And the testing of FPGA has become more and more important, especially the fault detection of local interconnect resources of FPGA. [0003] Generally speaking, FPGA testing is divided into intermediate testing and final testing, that is, testing when the FPGA chip is taped out without dicing and testing after dicing and pack...

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a configuration method of a field programmable gate array, to solve the technical problems of many times of configuration and many ports when detecting the failure of the local interconnection resources of the SRAM-based field programmable gate array, thereby improving the FPGA Efficiency of resource failure detection

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