Multi-channel Nand Flash controller and control method for same

Abstract

The invention relates to a multi-channel Nand Flash controller and a control method for the same. The multi-channel Nand Flash controller comprises a bus interface, an instruction receiving module, an instruction processing module, an IO (input / output) interface time sequence module and a data transmission module, wherein the instruction processing module is used for decomposing a received instruction into a plurality of micro instructions, scheduling the corresponding micro instructions for execution according to a preset algorithm, and performing corresponding operation on Nand Flash chips through the IO interface time sequence module according to the micro instructions. According to the multi-channel Nand Flash controller and the control method for the same, the instruction is decomposed into the micro instructions, dependence relationships among the micro instructions, the state of the interface bus and the states of the Nand Flash chips are dynamically analyzed, a cache is managed on the basis of the micro instructions, and the micro instructions are dynamically scheduled, so that requirements on the data cache can be reduced, and the performance under an external control instruction random request condition is improved.

Description

technical field [0001] The invention relates to the technical field of flash memory, in particular to a multi-channel Nand Flash controller and a control method thereof. Background technique [0002] NAND Flash is a non-volatile memory with a block page structure. Its storage space is composed of several storage blocks (Block), and each storage block is composed of several storage pages (Page). The storage page can be divided into two storage areas, the larger one is the data area, which is used to store data, and the smaller one is the spare area, which is usually used to store information such as ECC check codes. Take Micron's 32Gb flash memory chip MT29F32G08ABCAB as an example, the data organization unit is LUN, each LUN includes two Planes, each Plane contains 2048 blocks, each block contains 128 pages, and each page contains 8kB data area And the spare area of ​​448B. [0003] The NAND Flash structure can provide extremely high cell density, can achieve high storage ...

AI Technical Summary

Problems solved by technology

[0009] 5) There is a maximum number of write and erase operations for each block. After exceeding the limit, the probability of bad blocks will increase, and there will be a certain probability of bad blocks during normal operation;

[0020] 1) The logic complexity of the controller used is the same as that of controlling a single-chip Nand Flash, but the data bit width needs to be increased by N times;

[0021] 2) The IO pins of the controller occupy a lot;

[0022] 3) A large amount of cache is required, and its demand is N times that of a single-chip Nand Flash;

[0023] 4) The minimum reading and writing unit is N times that of a single chip, which is extremely inefficient for reading and writing small data;

[0024] 5) It is impossible to reduce the waiting time in the read, write and erase commands of the NF interface

[0025] 2. Organize Nand Flash in the way of M-level pipeline (that is, the control line and data line of each Nand Flash chip are common, and the chip selection signal is independent). When the wiping instructions are requested in random order, the controller cannot implement pipeline operation

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