A DMA transaction-level modeling method based on powerpc processor

Abstract

Provided is a DMA transaction-level modeling method based on a Power PC processor. Modeling is carried out on the basis of the system simulation verification platform Rabbits of a French TIMA laboratory. The method comprises a bus, an internal storage, peripheral equipment connected with the connecting bus, a DMA controller and a CPU, the bus is used for processing a transmission request of a primary equipment module, the internal storage is connected with the bus and used for storing data and instructions, the DMA controller is connected with the bus and used for controlling data transportation and sending interrupt request signals, the input end of the CPU is connected with the DMA controller to receive the interrupt request signals sent by the DMA controller, the CPU is connected with the bus and used for reading and writing the data and the instructions of the internal storage and reading and writing a register in the DMA controller and data in the peripheral equipment, Power PC instructions are simulated, and interrupt requests are processed. A DMA is programmed, the DMA is made to complete one or more data transportation tasks independently, platform operating speed can be improved conveniently, and the preliminary validation function of a platform is improved better.

Description

technical field [0001] The invention relates to a modeling method. In particular, it involves a DMA transaction-level modeling method based on PowerPC processors. Background technique [0002] With the development of SoC design, the design of software and hardware becomes more and more complicated, but the growth rate of the complexity of the software has greatly exceeded the increase of the complexity of the hardware. For complex SoC designs, in the early stage of building the entire system, it is necessary to evaluate the entire system architecture to determine whether the performance of the architecture meets the requirements. Because the traditional register transfer level (Register Transfer Level, RTL) design and verification can no longer meet the user's requirements for design time, manufacturing cost and product performance. The higher-level design method of Electronic System Level (ESL, Electronic System Level) is thus produced. ESL-based SoC design can effective...

AI Technical Summary

Problems solved by technology

However, the existing Qemu does not implement DMA, but does not model DMA, resulting in the inability to support DMA-related simulations

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