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Bonding pad structure and manufacturing method thereof

A technology for bonding pads and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve problems such as offset, uneven pressing, and long bonding time of integrated circuits and flexible circuit boards

Active Publication Date: 2017-02-22
SHANGHAI TIANMA MICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] (1) When the integrated circuit and the flexible circuit board (FPC) are connected to the module, it often causes deviation;
[0008] (2) When the bonding pad structure and the integrated circuit pad are pressed together, the pressing resistance is too large;
[0010] (4) When the bonding pad structure and the integrated circuit pad are pressed together, the two are unevenly pressed, poorly meshed, and the bonding time is long

Method used

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  • Bonding pad structure and manufacturing method thereof
  • Bonding pad structure and manufacturing method thereof
  • Bonding pad structure and manufacturing method thereof

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Embodiment Construction

[0058] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.

[0059] exist figure 2 A first embodiment of the invention is shown in .

[0060] figure 2 It is a schematic structural diagram of a bonding pad structure 200 according to the first embodiment of the present invention. Such as figure 2 As shown, the bonding pad structure 200 in this embodiment includes: a substrate 201 , a polysilicon layer 203 , a first metal layer 204 , a second metal layer 206 and a spacer layer. Wherein, the polysilicon layer 203 is arranged in strips and arranged in parallel on the subs...

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Abstract

The invention discloses a bond pad structure and a manufacturing method thereof. The bond pad structure includes: polysilicon layers arranged on a substrate in a strip shape in parallel; and first metal layers located on the polycilicon layers and second metal layers located on the first metal layers; and spacer layers arranged between the first metal layers and the second metal layers, wherein the spacer layers include a plurality of protruding blocks. The surfaces of the second metal layers are provided with a plurality of projections corresponding to the plurality of protruding blocks. The bond pad structure and the manufacturing method thereof improve a bond pad structure and realize a stronger acting force between the surface projections of the bond pad structure and bond lead-out points of an integrated circuit.

Description

technical field [0001] The invention relates to a semiconductor pad structure and a manufacturing method of the semiconductor pad structure, in particular to a bonding pad structure of an organic light emitting diode and a manufacturing method thereof. Background technique [0002] With the development of electronic products, semiconductor technology has been widely used in memory, central processing unit (CPU), liquid crystal display (LCD), light emitting diode (LED), organic light emitting diode (OLED), laser diode and other components or chipsets manufacturing. In order to achieve high integration and high speed, the size of semiconductor integrated circuits must be continuously reduced. Various materials and technologies have been proposed to achieve the above-mentioned goals of high integration and high speed, and to overcome the manufacturing obstacles associated therewith. To reduce the die size, pads (PADs) can be formed in the upper area where active, functional c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L51/52H01L51/56
CPCH01L24/03H01L24/05H01L24/11H01L24/14H01L2224/03H01L2224/0401
Inventor 李玉军郭峰赵本刚
Owner SHANGHAI TIANMA MICRO ELECTRONICS CO LTD