A method of manufacturing a semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises the steps of providing an insulator upper silicon wafer, forming a hard mask layer on a silicon layer in the insulator upper silicon wafer, patterning the hard mask layer, forming a plurality of core material layers which are isolated from one another, forming a patterned photoresist layer, enabling the photoresist layer to only cover part of the core material layers, executing the F-treatment process so as to increase the oxide growth selection ratio of the core material layers which are not covered with the photoresist layer relative to the core material layers covered with the photoresist layer, removing the photoresist layer, forming an oxide layer around the core material layers, etching the oxide layer, forming side walls on two sides of the core material layers, removing the core material layers, etching the silicon layer, forming Fins of FinFET, and removing the side walls. According to the method, on the premise of being compatible with the existing process, the formed FinFET has the Fins of different widths, and therefore the requirement for achieving different functions is met.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing process, in particular to a manufacturing method for forming a Fin Field Effect Transistor (FinFET) with fins (Fin) of different widths. Background technique [0002] Existing complementary metal-oxide-semiconductor (CMOS) transistors are two-dimensional, and as channel dimensions continue to shrink, the problems associated with short-channel effects become increasingly difficult to overcome. As a result, chipmakers are developing higher power-efficiency three-dimensional transistors, such as FinFETs, that better accommodate device scaling. In a FinFET, a fin-shaped channel standing on silicon-on-insulator (SOI) replaces the planar channel in traditional CMOS, and the gate is formed on and around the fin-shaped channel, which can provide more efficient electrostatic control ability. [0003] The width of the Fin formed by the existing FinFET manufacturing process is the same, and the purp...

AI Technical Summary

Problems solved by technology

[0002] Existing complementary metal-oxide-semiconductor (CMOS) transistors are two-dimensional, and as channel dimensions continue to shrink, problems related to short-channel effects become increasingly difficult to overcome

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