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Interconnect structure and method based on glass substrate

A technology of glass substrate and packaging method, which is applied in the direction of electrical components, electric solid devices, circuits, etc., can solve problems such as bump drop-off, undercutting, and narrow bump distance, and achieve the goal of reducing pitch, reducing cost, and shortening production time Effect

Active Publication Date: 2016-08-17
NAT CENT FOR ADVANCED PACKAGING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Especially for the etching of the seed layer, when the pitch of the bumps becomes smaller, the undercut is very serious, causing the bumps to fall off, and further reducing the distance between the bumps is restricted.

Method used

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  • Interconnect structure and method based on glass substrate
  • Interconnect structure and method based on glass substrate
  • Interconnect structure and method based on glass substrate

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0028] In the prior art, the process of processing bumps on glass substrates containing through holes is based on the sputtering seed layer and electroplating bumps, which have high manufacturing costs, long production cycles, and large bump spacing; and due to these There are many unfavorable factors in the method of the manufacturing process, which have a great impact on the manufacturing cost and production cycle of the product.

[0029] Such as Figure 4 Shown: in order to reduce the pitch and manufacturing time of the bumps on the surface of the glass substrate, and reduce the cost of production and processing, the present invention includes a glass substrate 1, the glass substrate 1 has a first main surface and a surface corresponding to the first main surface The second surface: the glass substrate 1 is provided with a conductive column 5 that penetrate...

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Abstract

The invention relates to an interconnection structure and method, in particular to an interconnection structure and method based on a glass substrate, and belongs to the technical field of microelectronic packaging. According to the technical scheme, the interconnection structure based on the glass substrate comprises the glass substrate, and the glass substrate is provided with a first main face and a second main face corresponding to the first main face; an electric conduction column penetrating through the interior of the glass substrate is arranged in the glass substrate, the first end of the electric conduction column is located on the first main face of the glass substrate, the second end of the electric conduction column penetrates out of the second main face of the glass substrate, and protruding points are formed outside the second main face of the glass substrate; the first end of the electric conduction column in the glass substrate is electrically connected with a wiring layer on the first main face of the glass substrate. The interconnection structure is simple and compact in structure, gaps between protruding blocks on the surface of the glass substrate can be reduced, the time for manufacturing glass through holes and the interconnection structure is greatly shortened, and meanwhile the cost for manufacturing surface protruding points is reduced to a great degree.

Description

technical field [0001] The invention relates to an interconnection structure and method, in particular to an interconnection structure and method based on a glass substrate, and belongs to the technical field of microelectronic packaging. Background technique [0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits has been continuously reduced, and the interconnection density has been continuously increased. At the same time, users' requirements for high performance and low power consumption have been continuously increased. In this case, the way to improve the performance by further reducing the line width of the interconnection is limited by the physical characteristics of the material and the equipment process, and the resistance-capacitance (RC) delay of the two-dimensional interconnection gradually becomes the limit to improve the performance of the semiconductor chip. bottleneck. The Through Glass Via (TGV) proc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/528H01L21/60
Inventor 姜峰李昭强
Owner NAT CENT FOR ADVANCED PACKAGING CO LTD