Memory data prefetch method and device

Abstract

The invention provides a method and a device for prefetching memory data. The method includes the following steps of sending a prefetching instruction to a memory; respectively writing N prefetching addresses in each item of an N-item first in first out (FIFO) queue; acquiring N data items stored in the N prefetching addresses from the memory in one time; and storing the N data items in each item of the N-item FIFO queue. N is greater than or equal to 1. The N-item FIFO queue can be filled only through one prefetching instruction, so that cross conflicts of multiple fetching requests from multiple FIFO queues in the prior art can be greatly reduced. Compared with the prior art, the method and the device have the advantages that at most N-1 times of page conflicts can be reduced, so that return time delay of the memory data can be greatly shortened, and consumption of memory power can be reduced.

Description

technical field [0001] The invention relates to computer storage technology, in particular to a memory data prefetch method and device. Background technique [0002] Prefetching technology is to use the time and space locality of the processor's memory access behavior to predict the required data before the processor cache memory is missing, and to retrieve it in advance to a location closer to the cache memory. When missing, check the prefetched address first, and return the data directly if it hits, which can greatly reduce memory access delays, reduce pipeline stalls caused by memory cache misses, and improve system performance. [0003] In order to reduce the impact on processor hardware design, a stream prefetch module (stream buffer) is usually added to the memory controller at present. Its main component is a first-in-first-out queue (FIFO, First Input FirstOutput). FIFO generally includes N entries, each containing an address location, a valid bit, and data for a ca...

AI Technical Summary

Problems solved by technology

[0004] For multiple sets of stream buffer structures, when there is a memory access conflict between memory access requests for data streams, multiple memory access conflict memory access requests interleaving access memory will result in a large number of page opening and page closing operations, increasing the time when memory data is returned latency while increasing memory power consumption

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