High Resolution Digital Pulse Width Modulator Based on Dual Frequency Multiphase Clock
A digital pulse width modulation, multi-phase clock technology, applied in the direction of pulse duration/width modulation, etc., can solve the problem of low resolution and achieve the effect of improving resolution
Active Publication Date: 2016-04-27
NORTHWESTERN POLYTECHNICAL UNIV
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Problems solved by technology
[0005] In order to overcome the deficiency of low resolution of the existing high-resolution digital pulse width modulator, the present invention provides a high-resolution digital pulse width modulator based on dual-frequency multi-phase clock
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[0023] The following examples refer to Figure 1-3 .
[0024]The high-resolution digital pulse width modulator based on the dual-frequency multi-phase clock of the present invention includes a data processing unit (Data_pro), two multi-phase clock arrays (Clk11array, Clk22array) of different frequencies, two counting units (Cnt1, Cnt2), Two value equality judgment units (Eqd1, Eqd2), two AND gate logic units (and1, and2) and one RS flip-flop (RStrigger). data_in[P0:0] is the digital signal input to DPWM, DPWM_out is the pulse width modulation signal output by DPWM, and data_in[P0:0] is proportional to the duty cycle of DPWM_out. The signal frequencies of the two multi-phase clock arrays Clk11array and Clk22array are different, but both have N×M phase clocks, and the duty cycle of each phase clock is 1 / (N×M). The above two multi-phase clock arrays are represented by Clk11array[0˜(N×M−1)] and Clk22array[0˜(N×M−1)] in the following.
[0025] The invention is based on the worki...
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The invention discloses a high-resolution digital pulse width modulator based on a double-frequency and multi-phase clock to solve the technical problem that an existing high-resolution digital pulse width modulator is low in resolution. According to the technical scheme, the high-resolution digital pulse width modulator comprises a data processing unit Data_pro, a multi-phase clock array Clk11array, a multi-phase clock array Clk22array, a counting unit Cnt1, a counting unit Cnt2, a numerical value equation judging unit Eqd1, a numerical value equation judging unit Eqd2, an and gate logical unit and1, an and gate logical unit and2 and an RS trigger. Two multi-phase clock arrays are obtained by carrying out phase shifting, frequency doubling and and processing on two clock signals with different frequencies. The counting clock at the corresponding phase position to carry out the logic operation according to input digital signals to obtain an output pulse width modulation signal with the corresponding duty ratio, and the resolution ratio of the digital pulse width modulator is increased.
Description
technical field [0001] The invention relates to a high-resolution digital pulse width modulator, in particular to a high-resolution digital pulse width modulator based on dual-frequency multi-phase clocks. Background technique [0002] In the DC-DC converter, increasing the switching frequency is conducive to the miniaturization and portability of the switching regulated power supply. For the digital DC-DC converter, in order to avoid the occurrence of the limit cycle phenomenon, the resolution of the digital pulse width modulator (DPWM:DigitalPulseWidthModulation) is required to be higher than that of the ADC. For example, for a DC-DC converter whose switching frequency is as high as several MHz, its switching period is only hundreds of nanoseconds, which poses a great challenge to the design of high-resolution DPWM. [0003] Common methods to realize DPWM include counter method and delay line method. In order to realize high-resolution DPWM, if the counter method is used...
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IPC IPC(8): H03K7/08
Inventor 魏廷存陈笑陈楠
Owner NORTHWESTERN POLYTECHNICAL UNIV