Method for processing carrier and method for fabricating charge storage memory element
A carrier and electrical technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as unreliable electrical contact of structural components
Active Publication Date: 2017-04-05
INFINEON TECH DRESDEN
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- Abstract
- Description
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- Application Information
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Problems solved by technology
Therefore, for structures where the lateral dimensions of the structural elements are not significantly larger than the electrical contactor itself, the electrical contact of the structural elements may be unreliable
Method used
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[0023] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.
[0024] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
[0025] The term "over" as used with reference to a deposited material formed "over" a side or surface or a deposited layer "over" a support may be used herein to mean that the deposited material may be formed "directly" on the indicated side, surface or "Above" a carrier, eg directly in contact with the indicated side, surface or carrier. The term "over" as used with reference to a deposited material formed "over" a side or surface or a deposited layer "over" a support may be used herein to mean that a deposited material may be formed...
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Abstract
The invention relates to methods for processing supports and methods for producing charge storage memory elements. A method for processing a carrier according to various embodiments may include forming a structure over the carrier, the structure including at least two adjacent structural elements, the at least two adjacent structural elements according to the distance between them A first distance arrangement; depositing a spacer layer above the structure, wherein the spacer layer may be deposited to have a thickness greater than half of the first distance, wherein the spacer layer may comprise a conductive spacer material; removing a portion of the spacer layer, wherein the separator material of the separator layer may remain in a region between said at least two adjacent structural elements; and electrically contact the remaining separator material.
Description
technical field [0001] Various embodiments generally relate to a method for processing a carrier, a method for fabricating a charge storage memory cell, a method for processing a chip, and a method for electrically contacting a separator structure. Background technique [0002] Fabricating an integrated circuit (also known as an IC, chip or microchip) typically involves multiple processes. One development in semiconductor processing is the scaling of integrated circuits to achieve the smallest practical feature sizes. Another driving factor for the semiconductor industry is to reduce production costs. One way to reduce costs can be directly related to the number of processes required, where it is often desirable to use only as few processes as possible. The reduced number of processes can not only Lowering costs, it can also increase yield, increase overall process reproducibility, minimize the number of defective structural elements, and can reduce the time for productio...
Claims
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IPC IPC(8): H01L21/768H01L21/28H01L29/423H01L21/336H01L27/11534
CPCH01L29/40114H01L29/40117H10B41/43H01L29/42324H01L29/4234H01L29/66825H01L29/66833H01L21/76895H01L21/76897H10B41/50H10B41/27H10B41/35H10B41/41
Inventor W.朗海因里希J.鲍威尔M.勒里希岑栢湛M.施蒂夫廷格R.施特伦茨
Owner INFINEON TECH DRESDEN