A multi-egress aggregation flow analysis method with an upper bound on the delay of on-chip network

Abstract

The invention relates to a multi-exit gather stream analyzing method for a network on chip delay bound. The multi-exit gather stream analyzing method is realized through the following steps: step a, confirming a target stream, to be more specific, selecting one stream to serve as the target stream, and enabling the other streams to serve as conflict streams; step b, searching the conflict streams and cutting into standard streams, finding all the conflict streams in a target stream route and cutting into I-type standard streams and II-type standard streams; step c, calculating a standard stream arrival curve so as to obtain the arrival curve of each type of standard streams; step d, calculating the bottleneck node of each sub-stream of each II-type standard stream; step e, calculating the target stream delay bound according to a formula. The multi-exit gather stream analyzing method for the network on chip delay bound is more precise to calculate the target stream delay at the analysis level, the analysis result is closer to the maximum delay obtained in performing practical simulation, and accordingly the network performance analysis is greatly facilitated.

Description

technical field [0001] The invention belongs to the technical field of network-on-chip (NoC) communication technology of integrated circuits, and relates to a multi-exit aggregation flow analysis method with an upper limit of network delay on chip. Background technique [0002] The paper "Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing" published on pages 123-132 of the 8th IEEE / ACM / IFIP international conference on Hardware / software codesign and system synthesis in 2012 used Fidler The model is used to calculate the upper bound of the target flow delay. This model is simple and easy to calculate; the shortcoming lies in the free parameter s that will be introduced in the process of calculating the equivalent service curve of the target flow i Both are set to zero, which leads to the model not being close to reality, resulting in the final delay upper bound is too large; "Performance Evaluation" 2006 pages 956-987 'Tight end-to-end per-flow d...

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Problems solved by technology

[0004] The purpose of the present invention is to provide a multi-exit aggregation flow analysis method for an upper bound of delay in an on-chip network, which solves the shortcoming of insufficient accuracy of the existing Fidler model when calculating the upper bound of delay. The beneficial effect of the present invention is to provide a method with Based on the multi-exit aggregation flow model, using network calculus as a tool, an analysis method for the upper bound of the on-chip network delay that is closer to the upper bound of the actual on-chip network target flow delay

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