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A global synchronization method and system based on packet switching system

A technology of packet switching and global synchronization, applied in time division multiplexing systems, synchronization devices, transmission systems, etc., can solve the problems of long time for reselecting the reference, congestion, complex calculation methods, etc., to reduce packet loss rate, Effect of Improving Calibration Accuracy

Active Publication Date: 2017-06-13
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The above calculation method is complicated, and the process of collecting status and issuing commands at the same time is long, especially when there may be thousands of chips in a large packet switching system
When a link or a chip in the system fails, the time to re-reference will be very long, which may cause system packet loss during this period or congestion due to time misalignment

Method used

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  • A global synchronization method and system based on packet switching system
  • A global synchronization method and system based on packet switching system
  • A global synchronization method and system based on packet switching system

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Embodiment Construction

[0069] The basic idea of ​​the present invention is: select a reference chip; each chip calibrates its own counter with the reference chip as a reference, wherein each chip sends a 0 time pulse or a 0 time pulse cell to all serdes, every Each chip also feeds back calibration cells according to the 0-time pulse or 0-time pulse cells received by each link.

[0070] figure 2 It is a schematic flow chart of the global synchronization method based on the packet switching system of the present invention, such as figure 2 As shown, the method includes:

[0071] Step 201: Select a reference chip.

[0072] Here, the selected reference chip may be: the reference chip is selected by each chip, or the reference chip is designated by the central processing unit CPU.

[0073] Step 202: Each chip calibrates its own counter based on the reference chip.

[0074] It should be noted that when the reference chip or the serdes connected to the reference chip fails, a new reference chip is se...

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Abstract

The invention discloses a global synchronization method based on a packet switching system. (serdes) sends out a 0-time pulse or 0-time pulse cell, and each chip also feeds back a calibration cell according to the 0-time pulse or 0-time pulse cell received by each link. The invention also correspondingly discloses a global synchronization system based on the packet switching system. Through the present invention, the packet loss rate can be reduced and the calibration accuracy can be improved.

Description

technical field [0001] The invention relates to the field of packet switching, in particular to a global synchronization method and system based on a packet switching system. Background technique [0002] The packet switching device is composed of the switching access chip SA and the switching chip SF on the line card. In the large-capacity packet switching system, the switching chip is composed of two levels, the uppermost layer is SF2, and the lower layer is SF1. system, it only needs to be composed of SA and SF2, and the structure of a global synchronization network is as follows figure 1 shown. In a distributed packet switching device, each line card needs to keep time stamp count synchronization, so as to ensure that the data packets sent by each line card at the same time have the same time stamp, so that they can be reassembled at the downstream destination line card. [0003] In the current global synchronization method, the method of selecting the benchmark is bas...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L7/00H04J3/06
CPCH04J3/0658H04L49/40H04L7/0016
Inventor 黄炜
Owner SANECHIPS TECH CO LTD