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Method to differentiate p-channel or n-channel devices based on different etch rates

A device and etching technology, applied in the field of semiconductor integrated circuits, can solve the problems of no IC surface preparation, SEM images cannot reveal details, etc.

Inactive Publication Date: 2016-09-21
芯片工程公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But in many instances, without proper IC surface preparation, SEM images do not reveal desired details

Method used

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  • Method to differentiate p-channel or n-channel devices based on different etch rates
  • Method to differentiate p-channel or n-channel devices based on different etch rates
  • Method to differentiate p-channel or n-channel devices based on different etch rates

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Embodiment Construction

[0021] In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of various embodiments. It should be apparent, however, to one skilled in the art that the disclosed embodiments may be practiced without these details. In other instances, well-known methods, procedures, and components have been described at a relatively high level and without detail in order to avoid obscuring aspects of the concepts. A number of descriptive terms and phrases are used to describe various embodiments of the present disclosure. These descriptive terms and expressions are used to convey meanings generally agreed to by those skilled in the art, unless a different definition is given in this specification. For clarity, some descriptive terms and phrases are presented in the following paragraphs. Reference is now made in detail to the examples illustrated in the accompanying drawings and discussed below.

[0022] ...

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Abstract

A method for determining whether a device on an existing CMOS integrated circuit is a p-channel device or an n-channel device. The method involves etching a contact etch stop layer (CESL) that occurs at different rates on the two different CESL types, thereby allowing the device type to be determined by examining how much unetched material remains.

Description

technical field [0001] This topic relates to semiconductor integrated circuits, and more specifically to determining whether a device on an existing CMOS integrated circuit is a p-channel device or an n-channel device. Background technique [0002] Integrated circuits (ICs) are often built on silicon wafers with active regions that are doped to provide excess holes for p-type regions and excess electrons for n-type regions. The active regions can be arranged to create p-channel metal-oxide field-effect transistors (p-MOSFET, PMOS or p-FET) and / or n-channel metal-oxide field-effect transistors (n-MOSFET, NMOS or n-FET ). In some cases, the active region can be built on a non-conductive layer such as silicon dioxide (SiO2), which can be placed between the active region and the silicon wafer. Many integrated circuits can utilize complementary metal-oxide-semiconductor (CMOS) circuits, which incorporate both p-FET and n-FET devices into the design. [0003] In most instances,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/26G01R31/307
CPCG01R31/307G01R31/2898
Inventor L.克利巴诺夫J.坎贝尔R.什卡拉特
Owner 芯片工程公司