Automatic testability model building method based on circuit simulation

A method of establishment, a technology of circuit simulation, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as high workload and error-prone, reduce difficulty and workload, and improve accuracy and effect. Effect

Inactive Publication Date: 2014-10-29
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Building a complete model is extremely labor-intensive and error-prone

Method used

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  • Automatic testability model building method based on circuit simulation
  • Automatic testability model building method based on circuit simulation
  • Automatic testability model building method based on circuit simulation

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0099] In order to illustrate the beneficial effect of the present invention, the present invention is verified experimentally by taking a filter circuit as an example. Figure 10 is the circuit diagram of the filter in the embodiment.

[0100] In this embodiment, Pspice software is used to store circuit information in its netlist file. The netlist file records information such as the devices existing in the circuit, the circuit nodes connected to the devices, and the values ​​of the devices. According to the internal storage format of the file, read the corresponding information. After running a simulation, the results of the run are stored in an output file (.out). The output file records information such as simulation time, netlist information, node voltage at the initial moment, and power, among which node voltage information needs to be read. Similar to reading the netlist, according to the output file format, read the node voltage information.

[0101] The content of ...

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Abstract

The invention discloses an automatic testability model building method based on circuit simulation. The automatic testability model building method comprises the steps of firstly, acquiring a relation between device information in a circuit and physical connection, performing faultless simulation on the circuit, performing fault simulation on devices in sequence, comparing voltages of nodes under faultless conditions with voltages of nodes under fault conditions to obtain an affectable node set of each device, taking each device as a module, calculating a fault transfer tree of each module according to the affectable node set of each device, setting element values in a directed main adjacent matrix according to the fault transfer trees to obtain a digraph model comprising the modules and the nodes, and removing nodes in the digraph model to obtain a final testability model. By means of the automatic testability model building method based on circuit simulation, the testability model of the circuit can be built automatically, manual difficulty and workload in function analysis on the circuit are greatly reduced, and modeling accuracy and effect are improved by means of circuit simulation.

Description

technical field [0001] The invention belongs to the technical field of testability models of electronic systems, and more specifically relates to a method for automatically establishing a testability model based on circuit simulation. Background technique [0002] With the continuous development of electronic technology, the complexity of electronic systems is increasing day by day, and testability analysis plays an increasingly important role in the fault diagnosis of complex electronic systems. Testability analysis depends on the testability model, and the accuracy of the testability model directly affects the analysis results. At present, the establishment of testability models often needs to rely on personnel's cognition and experience of system functions, and at the same time requires a huge amount of information. Building a complete model is extremely labor-intensive and error-prone. Therefore, it is necessary to study automatic modeling technology to complete the mo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 杨成林赵越刘震
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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