Metastability Detection and Correction in Analog-to-Digital Converters

Abstract

A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.

Description

technical field [0001] The present invention relates to methods and techniques that can be used to detect and / or correct metastable errors in ADCs. Background technique [0002] An analog-to-digital converter (ADC) is a device that converts an analog input signal into a corresponding digital output signal. Typically, this conversion is performed by comparing the analog input signal with one or more reference voltages using one or more comparators. The results of these comparisons are then stored in memory cells, such as latches or flip-flops. In most applications, the input signal is sampled at uniform time intervals to generate a sequence of digital values ​​representing the analog input signal. [0003] figure 1 is a block diagram showing a simplified example of a 1-bit ADC 100. In this example, an analog input signal is converted to 1-bit digital samples at regular intervals defined by a clock signal. [0004] refer to figure 1 , ADC100 includes a comparator 105 and...

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Problems solved by technology

However, in measurement instrumentation applications, such as real-time oscilloscopes, the required steady-state error rate can be very low (for example, 10 -20 ), the required sampling rate may be very high (eg, 10 or 100GS / s)

In these cases, it can be achieved by interleaving "M" ADCs, each operating at a lower sampling rate (f s / M) to reduce the metastable error rate, but this may lead to an unacceptably large interleaving factor M

Also, some ADC architectures are more prone to metastable errors than others, i.e. errors occur more frequently for a given sampling speed

This is one reason why e.g. pipelined ADCs are the preferred choice over SARADCs despite the generally superior power efficiency of SAR ADCs

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