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Sequential approximation analog to digital converter with digital correction and processing method thereof

An analog-to-digital converter, successive approximation technology, applied in analog/digital conversion, analog/digital conversion calibration/test, code conversion, etc. The effect of reducing errors

Inactive Publication Date: 2011-02-16
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to overcome the shortcoming that the coupling capacitor typesetting is difficult in the existing successive approximation analog-to-digital converters, and proposes a successive approximation analog-to-digital converter with digital correction

Method used

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  • Sequential approximation analog to digital converter with digital correction and processing method thereof
  • Sequential approximation analog to digital converter with digital correction and processing method thereof
  • Sequential approximation analog to digital converter with digital correction and processing method thereof

Examples

Experimental program
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Embodiment 1

[0033] Embodiment 1: It is assumed that the main DAC is composed of two stages, the upper 5-bit CDAC formed by the capacitor array and the lower 4-bit CDAC formed by the capacitor array.

[0034] figure 2 Schematic diagram of the structure of the calibration DAC and the comparator for the main DAC implemented in two stages, including the upper 5-bit CDAC 101, the lower 4-bit CDAC 103, and the 9-bit calibration DAC 104 and comparator 105 in the main DAC. The high-order CDAC 101 and the low-order CDAC 103 are coupled through a unit capacitor Cs, and the output of the calibration DAC 104 is coupled with the output of the main DAC through a capacitor Cc.

[0035] Assume that the individual capacitors of the high-order CDAC 101 are:

[0036] C 8 =(2 4 +ΔC 8 ) C, C 7 =(2 3 +ΔC 7 ) C, C 6 =(2 2 +ΔC 6 ) C, C 5 =(2+ΔC 5 ) C, C 4 =(1+ΔC 4 )C, where ΔC i is the error of each capacitor, and C is the unit capacitance.

[0037] Assume that the respective capacitances of the...

Embodiment 2

[0083] Embodiment 2: In order to improve the precision of the analog-to-digital converter and ensure a certain monotonicity, the main DAC may also include an intermediate M-bit RDAC composed of a resistor string, and its structural diagram is as follows Image 6 As shown, it includes the high 5-bit CDAC 101 in the main DAC, the middle 3-bit RDAC 102 , the low 4-bit CDAC 103 , and the 9-bit calibration DAC 104 and comparator 105 .

[0084] In RDAC 102, V Ri It is the voltage of a resistor in the resistor string (determined by 3-8Decoder A, the input signal of 3-8DecoderA is D4, D5, D6) close to the ground potential, V Ri+1 It is a resistor in the resistor string (determined by 3-8Decoder B, the input signal of 3-8Decoder B is D4, D5, D6) close to V ref voltage at one end. Therefore, V Ri and V Ri+1 They are:

[0085] V Ri = V ref ( D 6 ...

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Abstract

The invention discloses a sequential approximation analog to digital converter with digital correction and a processing method thereof aiming at the defect of difficult composition manufacture of a coupling capacitor in the traditional sequential approximation analog to digital converter. The sequential approximation analog to digital converter comprises a main DAC (Digital Analogue Converter), acalibration DAC, a comparer, a control circuit and a storage. The sequential approximation analog to digital converter is characterized in that the main DAC comprises a high-K-bit CDAC (Capacitance Digital Analogue Converter) and a low-N-bit CDAC. Introduced system errors and capacitance matching errors are digitally corrected and eliminated, error voltages corresponding to capacitors in the high-K-bit CDAC are quantized and stored in the storage, and two-digit 0 are added behind the tail of the quantized residual error voltage digital code and participate in the calculation of the error voltages. When normal conversion is carried out, the error voltage digital codes are accumulated and then last two digits are discarded, the remain digital codes are used as the input of the calibration DAC, thus the accuracy of the analog to digital converter is improved.

Description

technical field [0001] The invention belongs to the technical field of analog-to-digital conversion, and in particular relates to an analog-to-digital converter and a processing method thereof. Background technique [0002] The successive approximation analog-to-digital (A / D, Analog / Digital) converter has high precision and low power consumption. Although the conversion speed is slow, in many occasions that do not require high-speed conversion, such as touch screen control circuits, the successive approximation analog Digital converters have become a common choice. [0003] The traditional successive approximation A / D converter is usually implemented in a segmented manner, and there are generally several types: (1) the high K bit uses a switched capacitor array, and the low N bit uses a resistor string; (2) the high K bit uses a resistor string , the low N bit uses a switched capacitor array; (3) both the high K bit and the low N bit use a switched capacitor array. [0004...

Claims

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Application Information

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IPC IPC(8): H03M1/38H03M1/10
Inventor 于奇杜翎宁宁吴霜毅徐振涛李靖陈必江
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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