Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for improving operating efficiency of parallel architecture

A technology of operation efficiency and parallel processing, applied in the direction of concurrent instruction execution, machine execution device, resource allocation, etc., can solve the problems of reduced operation efficiency, unbalanced processing capacity among multiple channels, etc., to achieve the effect of improving processing efficiency

Inactive Publication Date: 2014-12-10
INSPUR GROUP CO LTD
View PDF3 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention provides a method for improving the operating efficiency of the parallel architecture, aiming at problems such as the unbalanced processing capabilities between multiple channels in the parallel computing architecture, which leads to the reduction of operating efficiency.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for improving operating efficiency of parallel architecture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0015] The advantages and design content of the method for improving the operating efficiency of the parallel architecture described in the present invention will be described in detail below through an embodiment.

[0016] The method for improving the operating efficiency of the parallel architecture described in this embodiment proposes a parallel processing module, the parallel processing module includes a message entry, a message exit, multiple data processing channels and a channel selection module, wherein various message Enter the parallel processing module through the message entrance, the channel selection module is a selector that allocates time according to the processing complexity, the message flow with higher complexity gets more processing time and less sending time window, the complexity Low message, get less processing time and more sending time window; After processing, various messages are sent out through the message exit.

[0017] as attached figure 1 As ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a method for improving operating efficiency of a parallel architecture. A data flow based flow equalizing algorithm is provided in the parallel computing architecture. The method comprises the steps of firstly determining channel priority levels according to processing capacities of channels, and determining the processing capacities required by data messages according to feature fields in data heads after receiving data; sending the data needing good processing capacities to high-priority-level channels to queue up; sequentially sending out the data according to data bulks in buffer areas of the channels different in priority level from large to small; firstly sending out the data in the high-priority-level channels under the same conditions. The requirement of the multichannel input and multichannel output computing architecture having priority level relation existing among the output channels can be met, and the processing efficiency of the parallel computing architecture is remarkably improved.

Description

technical field [0001] The invention relates to a parallel computing architecture, in particular to a method for improving the operating efficiency of the parallel architecture. Background technique [0002] In the parallel computing architecture, the data processing chip receives data from multiple channels and performs parallel processing, thereby greatly improving the data processing efficiency. In the parallel computing architecture, the processing speed of multiple channels is different, which will lead to the reduction of parallel processing efficiency. Therefore, improving the balance of processing capabilities between multiple channels can significantly improve the efficiency of parallel processing. The processing capacity balancing algorithm among multiple channels is one of the core algorithms to ensure the efficient operation of the parallel processing architecture. [0003] At present, the most common equalization algorithm is the round-robin average algorithm....

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F9/38G06F9/50
Inventor 毕研山于治楼姜凯
Owner INSPUR GROUP CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com