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Microprocessor and its configuration method

A microprocessor and processor technology, applied in electrical digital data processing, instruments, computers, etc., can solve the problems of inability to provide speed, accuracy, system level transparency, etc., and achieve the effect of less power consumption

Active Publication Date: 2018-09-21
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This may be sufficient for many purposes, but may not provide otherwise desired speed, accuracy, and / or system-level transparency

Method used

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  • Microprocessor and its configuration method
  • Microprocessor and its configuration method
  • Microprocessor and its configuration method

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Embodiment Construction

[0042] The following describes the preferred embodiment of the present invention. Each embodiment is used to illustrate the principles of the present invention, but not to limit the present invention. The scope of the present invention should be determined by the claims.

[0043] Please refer to figure 1 , which is a block diagram showing a multi-core microprocessor 100 . The microprocessor 100 includes a plurality of processing cores, labeled 102A, 102B to 102N, collectively referred to as the plurality of processing cores 102 , or simply the plurality of cores 102 , and individually referred to as the processing cores 102 or simply the cores 102 . More preferably, each core 102 includes a pipeline of one or more functional units (not shown in the figure), which includes an instruction cache (instruction cache), an instruction conversion unit or an instruction decoder, and more preferably includes A microcode unit, temporary renaming unit, reservation station, cache memory...

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Abstract

The present invention provides a microprocessor and a configuration method of the microprocessor. The microprocessor includes an instruction and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the above instruction. When the above instruction indicated a first predetermined value, the plurality of processing cores are configured to jointly appoint one preset processing core among the plurality of processing cores to be a guiding processor. When the above instruction indicates a second preset value differing from the first preset value, the plurality of processing cores are configured to jointly appoint addition one preset processing core among the plurality of processing cores apart from the above guiding processor to be a guiding processor. The present invention has less power consumption.

Description

technical field [0001] The present invention relates to a microprocessor, and in particular to dynamic assignment of boot processors in a multi-core microprocessor. Background technique [0002] The increase in multi-core microprocessors is mainly due to the advantages in performance they provide. This may be primarily due to the rapid reduction in the size of semiconductor device geometries, thereby increasing transistor density. The presence of multiple cores in a microprocessor has created a need for one core to communicate with other cores to perform various functions such as power management, cache memory management, debugging and configuration related to more cores. [0003] Traditionally, programs (eg, operating systems or applications) running on architectures on multi-core processors have communicated using semaphores located in a system memory architecturally addressable by all cores. This may be sufficient for many purposes, but may not provide other desired spe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/177
Inventor G·葛兰·亨利史蒂芬·嘉斯金斯
Owner VIA TECH INC