Unlock instant, AI-driven research and patent intelligence for your innovation.

A kind of nand flash memory and preparation method thereof

A technology of flash memory and control gate, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., and can solve problems such as incompatibility of NAND flash memory technology

Active Publication Date: 2017-02-15
SHANGHAI XINCHU INTEGRATED CIRCUIT
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention proposes a two-dimensional NAND-type flash memory technology based on the Gate Last (gate last technology) metal gate technology. The metal gate technology is used to realize the control gate of the NAND unit instead of the traditional polysilicon surrounding the control gate. The integration of dielectric constant metal gate advanced CMOS process is compatible with the current mainstream Gate Last CMOS process, and overcomes the problem that the current NAND flash memory process cannot be compatible with advanced standard logic processes

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A kind of nand flash memory and preparation method thereof
  • A kind of nand flash memory and preparation method thereof
  • A kind of nand flash memory and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] A two-dimensional NAND flash memory process based on the GateLast (gate last) metal gate process proposed by the present invention, wherein the high-voltage DMOS (Doublediffusion metal-oxide-semiconductor, double diffused metal-oxide semiconductor) device is an example of an N-type MOS, The process steps of the P-type MOS transistor are similar, and the present invention emphasizes the compatibility with the standard metal gate CMOS process, which will not be repeated here. refer to Figure 1a ~ Figure 11b Shown is the preparation flow chart of the present invention, wherein the left figure a is a cross-sectional view along the direction of the NAND array bit line, and the right figure b is a cross-sectional view along the direction of the NAND array word line. The specific implementation includes the following steps.

[0048] Step S1: provide a substrate 1, a single crystal silicon wafer can be used as the starting substrate 1, the silicon wafer can be a single-layer stru...

Embodiment 2

[0069] Simultaneously the present invention also provides a kind of NAND flash memory 1000, as Figure 12a and 12b as shown, Figure 12a is a cross-sectional view along the bit line direction of the NAND array, Figure 12b is a cross-sectional view along the word line direction of the NAND array.

[0070] The NAND flash memory 1000 includes a substrate 100 , the upper surface of the substrate 100 is covered with a high dielectric constant material layer 102 . An active area (AA) and an isolation area 101 are arranged in the substrate 100 located in the CMOS circuit area 1-A and the memory cell array area 1-B;

[0071]A source (S) and a drain (D) are formed in the substrate in the CMOS circuit region, and a gate 108 is formed on the substrate 100 in the CMOS circuit region 1-A. Wherein, the source is close to the gate 108, thereby ensuring that the device has good conduction characteristics; and an isolation region 101 is provided between the drain and the gate 108 to impro...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a two-dimensional NAND flash memory based on a Gate Last metal gate technology. A control gate of an NAND unit rather than a traditional polycrystalline silicon surrounded control gate is achieved through the metal gate technology, the NAND flash memory technology can be integrated with an advanced high-dielectric-constant metal gate CMOS technology and can be compatible with a current mainstream Gate Last CMOS technology, and the problem that an existing NAND flash memory technology can not be compatible with an advanced standard logic technology is solved. Meanwhile, a method for achieving a high-voltage DMOS device in the advanced high-dielectric-constant metal gate CMOS technology is provided, and therefore the flashable operation of the NAND flash memory can be achieved.

Description

technical field [0001] The invention relates to a semiconductor device preparation process, in particular to a two-dimensional NAND flash memory process based on a Gate Last metal gate process. Background technique [0002] NAND flash memory has become the current mainstream non-volatile storage technology and is widely used in data centers, personal computers, mobile phones, smart terminals, consumer electronics and other fields, and the demand is still growing. The manufacturing process of NAND flash memory has also been developed to 16nm, transforming from a two-dimensional manufacturing process to a three-dimensional manufacturing process. Samsung has announced the commercial production of 128Gb 24-cell stacked 3D NAND chips. Micron announced a new 16nm128Gb two-dimensional NAND chip, using a new two-dimensional cell structure to break through the size reduction limit of the traditional two-dimensional structure. [0003] However, neither the traditional two-dimensiona...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L21/8247
Inventor 亢勇陈邦明
Owner SHANGHAI XINCHU INTEGRATED CIRCUIT