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Method and multi-thread processing system for updating shared cache memory

A multi-threaded processor and high-speed buffering technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve problems such as dynamic changes in data attributes that cannot be solved

Active Publication Date: 2017-05-24
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As can be seen, such dynamic shifts of data attributes among threads cannot be accounted for by static partitioning that locks the threads to be allocated in a predefined portion of the cache

Method used

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  • Method and multi-thread processing system for updating shared cache memory
  • Method and multi-thread processing system for updating shared cache memory
  • Method and multi-thread processing system for updating shared cache memory

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Embodiment Construction

[0019] Several aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternative embodiments may be devised without departing from the scope of the present invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.

[0020] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the invention. ...

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Abstract

Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

Description

technical field [0001] The disclosed embodiments are directed to cache allocation in a shared cache. More specifically, the exemplary embodiments are directed to the allocation of cache lines in a shared partitioned cache in a multithreaded processor. Background technique [0002] The manifestation of multithreading in a processor can occur at different levels or with different processing granularities. Individual threads of a multithreaded processor may share one or more levels of cache and memory. The threads may have different data attributes, such as "streaming data", "localized data", "multipurpose data", "shared", "non-shared", etc. Simple allocation and replacement schemes such as least recently used (LRU) are not suitable because of the different contexts created by the threads and thread-specific data attributes that must be resolved. [0003] For example, in the absence of a dedicated allocation / replacement mechanism, a cache line of a shared cache that has been...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0842G06F12/0846
CPCG06F12/0842G06F12/0848G06F12/0864
Inventor 克里斯托弗·爱德华·科布阿贾伊·阿南特·英格尔卢奇安·科德雷斯库苏雷什·K·文库马汉提
Owner QUALCOMM INC