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Element-embedded package structure, semiconductor device and manufacturing method thereof

A packaging structure, embedded technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components and other directions

Active Publication Date: 2017-11-14
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, the electrical grounding design of such semiconductor packages and / or semiconductor components still needs to be considered

Method used

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  • Element-embedded package structure, semiconductor device and manufacturing method thereof
  • Element-embedded package structure, semiconductor device and manufacturing method thereof
  • Element-embedded package structure, semiconductor device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0014] Please refer to figure 1 , which shows a cross-sectional view of an embodiment of the component embedded packaging structure according to the present invention. The component embedded package structure 100 includes a die 102, a die holder 104, a first lead 106, a second lead 108, a first dielectric layer 110, a patterned conductive layer 112, a second dielectric layer 114 and a conductive Layer 116.

[0015] The die 102 has an active surface 102 a and a back surface 102 b opposite to the active surface 102 a. The die 102 may have pads 103 electrically connected to the outside, and the backside 102 b of the die may be attached to the die paddle 104 through an adhesive layer 118 .

[0016] The first pin 106 and the second pin 108 are disposed around the die paddle 104 . The first pin 106 has a first surface 106a, a second surface 106b and an outer surface 106c connecting the first surface 106a and the second surface 106b. The second pin 108 has a first surface 108a, a...

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PUM

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Abstract

The present invention provides a component embedded packaging structure, its semiconductor device and its manufacturing method. The component embedded packaging structure includes: a bare chip placed on a bare chip holder; a first lead and a second lead, disposed around the die holder; the first dielectric layer covers the die, the die holder, the first lead and the second lead, and has a first through hole exposing at least part of the die, and a second A through hole exposing at least part of the second pin, wherein one side of the first dielectric material is substantially flush with one side of the first pin; a patterned conductive layer is disposed on the upper surface of the first dielectric layer, and electrically connected to the bare chip through the first through hole, and electrically connected to the second pin through the second through hole; the second dielectric layer is disposed on the first dielectric layer and covers the patterned conductive layer; and the conductive layer , covering the upper surface and side surfaces of the second dielectric layer and the side surfaces of the dielectric layer, and directly contacting the side surfaces of the first pins.

Description

technical field [0001] The invention relates to a semiconductor package and a manufacturing method thereof. Background technique [0002] Due to the need to increase the process speed and reduce the size, semiconductor packaging has become very complicated. When the process speed increases and the benefits of small size increase significantly, the characteristics of the semiconductor package also have problems. In particular, higher clock speeds lead to more frequent transitions between signal levels, thus resulting in higher intensity electromagnetic emissions at high frequencies or short waves (electromagnetic emission). Electromagnetic emissions can radiate from semiconductor packages and adjacent semiconductor components. If the intensity of the electromagnetic radiation adjacent to the semiconductor device is high, the electromagnetic radiation negatively affects the operation of the device in the semiconductor package (ie, electromagnetic interference (EMI)). In pa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L21/56
CPCH01L24/82H01L24/97H01L2224/04105H01L2224/24246H01L2224/32245H01L2224/73267H01L2224/92244H01L2224/97H01L2924/3025H01L2224/8203H01L2224/24H01L2224/83H01L2224/82H01L2924/00012
Inventor 林弈嘉廖国宪李明锦
Owner ADVANCED SEMICON ENG INC