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Packaging assembly manufacturing method

A technology of packaging components and packaging materials, which is applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., and can solve the problems of complex manufacturing process and cost increase of multi-layer packaging components

Active Publication Date: 2019-05-07
SILERGY SEMICON TECH (HANGZHOU) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In view of this, the object of the present invention is to provide a method for manufacturing packaged components to solve the problem of increased cost due to the complexity of the manufacturing process of multilayer packaged components

Method used

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Embodiment Construction

[0032] Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. For simplicity, the package structure obtained after several steps can be described in one figure.

[0033] It should be understood that when describing a package structure, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may refer to being directly on another layer or another region, or on There are other layers or regions between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region. If it is to describe the situation directly on another layer or another area, the expression "directly on" or "on and adjacent to" ...

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Abstract

Disclosed is a packaging assembly manufacturing method, including: forming a lead frame on a substrate, wherein the lead frame includes a plurality of leads with exposed first surfaces; mounting a plurality of layers of electronic components on the lead frame, so that the electronic component on at least one layer is electrically connected with the first surfaces of at least one group of leads inthe plurality of leads; and removing at least portion of the substrate, so that second surfaces of the plurality of leads opposite the first surfaces are exposed for external connection. According tothe method, the semiconductor structure does not need to be overturned in the manufacturing process, the yield of the packaging assembly can be improved, the cost is reduced, and the packaging qualityis improved.

Description

technical field [0001] The present invention relates to semiconductor packaging, and in particular to a method of manufacturing a packaging assembly. Background technique [0002] With the increasing demand for miniaturization, light weight and multi-functionalization of electronic components, the requirements for semiconductor packaging density are getting higher and higher, so as to achieve the effect of reducing the package size. Therefore, a package assembly using a lead frame and containing multiple semiconductor dies has become a new hot spot. In such packages, the configuration of the plurality of semiconductor dies and their connection methods have a critical impact on the size and performance of the package. [0003] Stacked multilayer package assemblies have been proposed in which multiple semiconductor dies are stacked on the same lead frame. The lowermost semiconductor die can be directly attached to the lead frame by solder. The semiconductor die on the upper...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L21/58
CPCH01L2224/16
Inventor 谭小春申屠军立叶佳明
Owner SILERGY SEMICON TECH (HANGZHOU) CO LTD
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