Floating-point adder circuitry

Abstract

An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.

Description

[0001] This application claims priority to US Patent Application No. 14 / 019,196, filed September 5, 2013, which is hereby incorporated by reference in its entirety. technical field

[0002] The present invention relates to performing floating point arithmetic operations in integrated circuits, and more particularly to dynamic bit extension and shifting techniques for floating point operations. Background technique

[0003] Floating point arithmetic is generally implemented according to the IEEE754 standard, which defines floating point numbers as having a sign, mantissa, and exponent, with the requirement that the mantissa be always normalized because the standard implies a leading "1". However, performing normalization can be expensive in terms of circuit area as well as operational latency. Some floating-point operations also require that floating-point operands be manipulated as part of the floating-point operation. For example, floating-point addition and subtraction re...

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