Methods and structures for carrying integrated circuits

Abstract

In one embodiment, a tray that includes a dielectric frame structure, a re-adherable pad and a marking is disclosed. The dielectric frame structure includes a recessed region where the re-adherable pad is formed. A plurality of integrated circuits is placed on a re-adherable surface of the re-adherable pad. The marking on the dielectric frame that is reflective of a given input-output pin position for each integrated circuit in the plurality of integrated circuits in the tray. In addition to that, two methods are also disclosed. First, a method of handling the integrated circuits using the tray is disclosed. Second, a method of forming the tray is also disclosed.

Description

[0001] This application claims priority to US Patent Application 14 / 470,742, filed August 27, 2014, and US Provisional Patent Application 61 / 873,168, filed September 3, the entire contents of which are incorporated herein by reference. technical field Background technique [0002] An integrated circuit may be fabricated at one location (ie, a wafer fabrication facility) but packaged at another location (ie, a test and assembly facility). Different wafer fabs often use different process technologies to fabricate integrated circuits. In this case, the partially formed integrated circuit or partially formed integrated circuit package is sent to a semiconductor fabrication facility so that the partially formed device can be further processed. [0003] However, the transfer of integrated circuit chips from one factory to another is vulnerable because of the increased shipping and handling procedures involved in loading and unloading integrated circuits. For example, integrated c...

AI Technical Summary

Problems solved by technology

However, the state of current technical procedures still results in over 30% of integrated circuits being damaged due to improper handling

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