Method for forming shallow trench isolation structure

Abstract

The invention discloses a formation method for a shallow trench isolation structure. The formation method comprises the step of carrying out an ion implantation treatment on a semiconductor substrate at the corner of a shallow trench isolation area after forming the shallow trench isolation area, wherein stress at the corner can be reduced, thus a third dielectric layer is subsequently formed at the corner and not liable to break through, and then the performance of a device is improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a shallow trench isolation structure. Background technique [0002] Shallow trench isolation structures are usually formed in a semiconductor substrate, and filled with a dielectric layer for isolating semiconductor devices. The steps of forming the shallow trench isolation structure in the prior art include: [0003] A semiconductor substrate 10 is provided, and an oxide layer 20 and a hard mask layer 30 are sequentially formed on the semiconductor substrate 10, such as figure 1 shown; [0004] Etching the mask layer 30, the oxide layer 20, and the semiconductor substrate 10 in sequence to form shallow trench isolation regions 11 to expose the semiconductor substrate 10, such as figure 2 shown; [0005] A liner oxide layer 40 is formed on the surface of the semiconductor substrate 10 exposed by the trench isolation region 11, such as image 3...

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Problems solved by technology

However, due to the corners of the shallow trench isolation structure 50 and the semiconductor substrate 10 (such as Figure 5 The silicon dioxide formed by the dotted line) is relatively thin, and the stress at the corner is relatively large; therefore, when the device is energized to test the breakdown resistance of the oxide layer 20, the silicon dioxide at the corner is usually the weakest and the most The part that is easy to be broken down will cause the performance of the device to be unstable, which is not conducive to improving the overall stability of the semiconductor device

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